Renesas RX600 Series, User Manual

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RX610 Group 11. Buses
R01UH0032EJ0120 Rev.1.20 Page 284 of 1006
Feb 20, 2013
(3) Tn1 to Tnm (clock cycles of CS extension)
In the case of normal access, Tn1 to Tnm represent the clock cycles of the period following the cycle where the strobe
signal is valid (Tend) up to negation of the CSi# signal. For read or write access, the timing of negation is controlled by
the CS extension cycles setting for reading (CSROFF) or the CS extension cycles setting for writing (CSROFF) in CSi
wait control register 2 (CSiWCNT2).
The number of cycles is counted from the cycle following the cycle where the strobe signal is valid.
In the case of page access, Tn1 to Tnm represent the clock cycles of the period for the cycle following the last cycle
where the strobe signal is valid up to negation of the CSi# signal.
For write access, the setting for write data output extension cycles (WDOFF) controls extension of the period where the
address and output data are valid.
(4) Th (address hold time)
In the clock cycle that follows the end of the cycles of CS extension, the value for the address is retained from the
previous access. However, when two or more rounds of external bus access are required in response to a request for
transfer from a bus master, only the value from the final bus access of the divided-up operation is retained. In bus access
other than the final bus access, the address value is updated to that for the next access operation at the time of negation of
the CS# signal. In the case of normal access, one clock cycle is inserted as the period of negation of the CSi# signal. In
the case of page access, a period for negation of the CS# signal is not inserted (see figures 11.10 and 11.11).
(5) Tdw1 to Tdwn (write-data output extension clock cycles)
For write access, if the setting for write-data output extension wait is a value other than zero, clock cycles of write-data
output extension are inserted from the cycle that follows the cycle where the strobe signal is valid (Tend).
In the case of normal access, this is inserted within the period of clock cycles of CS extension (point 3. above).
In the case of page access, this is inserted within the period of the cycle where the strobe signal is valid and subsequent
page access or within the period of clock cycles of CS extension (point 3. above). Valid address and data output are
extended over this period, and the WRi# and WR# signals are negated.
(6) Tpw1 to Tpwn (page-read cycle or page-write cycle wait)
For the second and subsequent cycles of the bus clock during page access, the values for a page-read cycle wait or
page-write cycle wait are used instead of the settings for a normal read or write cycle wait. The setting for the wait until
WR assertion becomes effective is in a similar way as for the first round of access. How the setting for RD assertion
controls operation differs with the setting for page-read access mode (CSiMOD.PRMOD) as described below.
CSiMOD.PRMOD = 0: A wait until RD assertion is inserted in a similar way as for the first round of access, and the
RD# signal is negated.
CSiMOD.PRMOD = 1: Although a wait until RD assertion is inserted in a similar way as for normal-access
compatibility mode, the RD# signal continues to be asserted over this period.