Renesas RX600 Series, User Manual

Page: 288 / 1006

RX610 Group 11. Buses
R01UH0032EJ0120 Rev.1.20 Page 288 of 1006
Feb 20, 2013
Chip select
(CSn#)
Data read
(RD#)
Normal read cycle wait
(CSRWAIT): 2
RD assert wait (RDON): 1
D1
A2
A1
Tw1 Tend Tw2 Tw1 Tw2
D2
Tend
Read-access CS extension cycle (CSROFF): 1
Tn1
CSRWAIT: 2
CSROFF: 1
RDON: 1
Tn1
Byte control 1
(BC1#)
Byte control 0
(BC0#)
HiZ
Th Th
Data bus
(D15 to D8)
External bus clock
(BCLK)
Address
(A23 to A0)
[Legend] n = 0 to 7
Data bus
(D7 to D0)
Figure 11.12 Example of Normal-Read Operation (when 16-Bit Bus Space is Accessed in 8 Bits)
Normal write cycle wait (CSWWAIT): 2
CS assert wait
(CSON): 0
WR assert wait (WRON): 1
A2
A1
Tw1 Tend Tw2 Tw1 Tw2 Tend Tn1
CSWWAIT: 2
CSWOFF: 1
Tn1
Write data output wait (WDON): 1
D1
D2
Write-access CS extension cycle (CSWOFF): 1
Write data output extension cycle (WDOFF): 1
Data write 1
(WR1#)
Th
Data write 0
(WR0#)
Th
WRON: 1
WDOFF: 1
WDON: 1
Chip select
(CSn#)
Data bus
(D15 to D8)
External bus clock
(BCLK)
Address
(A23 to A0)
Data bus
(D7 to D0)
[Legend] n = 0 to 7
Figure 11.13 Example of Normal-Write Operation (when 16-Bit Bus Space is
Accessed in 8 Bits, in Byte Strobe Mode)