OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2-34
Based index addressing generates an effective address that is the sum of a base register, an index
register and a displacement (see Figure 2-19). The two address components can be determined at
execution time, making this a very flexible addressing mode.
Figure 2-19. Based Index Addressing
Based index addressing provides a convenient way for a procedure to address an array located on
a stack (see Figure 2-20). The BP register can contain the offset of a reference point on the stack.
This is typically the top of the stack after the procedure has saved registers and allocated local
storage. The offset of the beginning of the array from the reference point can be expressed by a
displacement value. The index register can be used to access individual array elements. Arrays
contained in structures and matrices (two-dimensional arrays) can also be accessed with based
indexed addressing.
String instructions do not use normal memory addressing modes to access operands. Instead, the
index registers are used implicitly (see Figure 2-21). When a string instruction executes, the SI
register must point to the first byte or word of the source string, and the DI register must point to
the first byte or word of the destination string. In a repeated string operation, the CPU will auto-
matically adjust the SI and DI registers to obtain subsequent bytes or words. For string instruc-
tions, the DS register is the default segment register for the SI register and the ES register is the
default segment register for the DI register. This allows string instructions to operate on data lo-
cated anywhere within the 1 Mbyte address space.
EA
BP
BX
SI
DI
Opcode
Mod R/M
Displacement
or
or
+
+
A1022-0A
Summary of Contents for 80C186XL
Page 1: ...80C186XL 80C188XL Microprocessor User s Manual...
Page 2: ...80C186XL 80C188XL Microprocessor User s Manual 1995...
Page 18: ...1 Introduction...
Page 19: ......
Page 27: ......
Page 28: ...2 Overview of the 80C186 Family Architecture...
Page 29: ......
Page 79: ......
Page 80: ...3 Bus Interface Unit...
Page 81: ......
Page 127: ......
Page 128: ...4 Peripheral Control Block...
Page 129: ......
Page 137: ......
Page 138: ...5 ClockGenerationand Power Management...
Page 139: ......
Page 154: ...6 Chip Select Unit...
Page 155: ......
Page 178: ...7 Refresh Control Unit...
Page 179: ......
Page 193: ......
Page 194: ...8 Interrupt Control Unit...
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Page 227: ......
Page 228: ...9 Timer Counter Unit...
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Page 253: ......
Page 254: ...10 Direct Memory Access Unit...
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Page 283: ......
Page 284: ...11 Math Coprocessing...
Page 285: ......
Page 302: ...12 ONCE Mode...
Page 303: ......
Page 306: ...A 80C186 Instruction Set Additions and Extensions...
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Page 318: ...B Input Synchronization...
Page 319: ......
Page 322: ...C Instruction Set Descriptions...
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Page 371: ......
Page 372: ...D Instruction Set Opcodes and Clock Cycles...
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Page 396: ...Index...
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