Intel 80C186XL, User Manual

Page: 76 / 405

2-47
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Only the single step exception can occur concurrently with another exception. At most, two ex-
ceptions can occur at the same instruction boundary and one of those exceptions must be the sin-
gle step. Single step is a special case; it is discussed on page 2-48. Ignoring single step (for now),
only one exception can occur at any given instruction boundary.
An exception has priority over both NMI and the maskable interrupt. However, a pending NMI
can interrupt the CPU at any valid instruction boundary. Therefore, NMI can interrupt an excep-
tion service routine. If an exception and NMI occur simultaneously, the exception vector is taken,
then is followed immediately by the NMI vector (see Figure 2-28). While the exception has high-
er priority at the instruction boundary, the NMI interrupt service routine is executed first.
Figure 2-28. Simultaneous NMI and Exception
NMI
F = 1
Divide Error
Push PSW, CS, IP
Fetch NMI Vector
Execute NMI
Service Routine
Push PSW, CS, IP
Fetch Divide Error Vector
Execute Divide
Service Routine
IRET
IRET
Divide
A1031-0A