C-31
INSTRUCTION SET DESCRIPTIONS
NEG
Negate:
NEG
dest
Subtracts the destination operand,
which may be a byte or a word, from 0
and returns the result to the desti-
nation. This forms the two's
complement of the number, effectively
reversing the sign of an integer. If the
operand is zero, its sign is not
changed. Attempting to negate a byte
containing –128 or a word containing –
32,768 causes no change to the
operand and sets OF.
Instruction Operands:
NEG reg
NEG mem
When Source Operand is a Byte:
(dest)
←
FFH – (dest)
(dest)
←
(dest) + 1 (affecting flags)
When Source Operand is a Word:
(dest)
←
FFFFH – (dest)
(dest)
←
(dest) + 1 (affecting flags)
AF
ü
CF
ü
DF –
IF –
OF
ü
PF
ü
SF
ü
TF –
ZF
ü
NOP
No Operation:
NOP
Causes the CPU to do nothing.
Instruction Operands:
none
None
AF –
CF –
DF –
IF –
OF –
PF –
SF –
TF –
ZF –
NOT
Logical Not:
NOT dest
Inverts the bits (forms the one's
complement) of the byte or word
operand.
Instruction Operands:
NOT reg
NOT mem
When Source Operand is a Byte:
(dest)
←
FFH – (dest)
When Source Operand is a Word:
(dest)
←
FFFFH – (dest)
AF –
CF –
DF –
IF –
OF –
PF –
SF –
TF –
ZF –
Table C-4. Instruction Set (Continued)
Name
Description
Operation
Flags
Affected
NOTE:
The three symbols used in the Flags Affected column are defined as follows:
– the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
ü
the flag is updated after the instruction is executed
Summary of Contents for 80C186XL
Page 1: ...80C186XL 80C188XL Microprocessor User s Manual...
Page 2: ...80C186XL 80C188XL Microprocessor User s Manual 1995...
Page 18: ...1 Introduction...
Page 19: ......
Page 27: ......
Page 28: ...2 Overview of the 80C186 Family Architecture...
Page 29: ......
Page 79: ......
Page 80: ...3 Bus Interface Unit...
Page 81: ......
Page 127: ......
Page 128: ...4 Peripheral Control Block...
Page 129: ......
Page 137: ......
Page 138: ...5 ClockGenerationand Power Management...
Page 139: ......
Page 154: ...6 Chip Select Unit...
Page 155: ......
Page 178: ...7 Refresh Control Unit...
Page 179: ......
Page 193: ......
Page 194: ...8 Interrupt Control Unit...
Page 195: ......
Page 227: ......
Page 228: ...9 Timer Counter Unit...
Page 229: ......
Page 253: ......
Page 254: ...10 Direct Memory Access Unit...
Page 255: ......
Page 283: ......
Page 284: ...11 Math Coprocessing...
Page 285: ......
Page 302: ...12 ONCE Mode...
Page 303: ......
Page 306: ...A 80C186 Instruction Set Additions and Extensions...
Page 307: ......
Page 318: ...B Input Synchronization...
Page 319: ......
Page 322: ...C Instruction Set Descriptions...
Page 323: ......
Page 371: ......
Page 372: ...D Instruction Set Opcodes and Clock Cycles...
Page 373: ......
Page 396: ...Index...
Page 397: ......