Intel 80C186XL, User Manual

Page: 164 / 405

6-9
CHIP-SELECT UNIT
Figure 6-7. MMCS Register Definition
Register Name: MCS Control Register
Register Mnemonic: MMCS
Register Function: Controls the operation of the MCS chip-selects.
Bit
Mnemonic
Bit Name
Reset
State
Function
U19:13 Start
Address XXH Defines the starting address for the block of
MCS chip-selects. During memory bus cycles,
U19:13 are compared with the A19:13 address
bits. An equal to or greater than result enables
the MCS chip-select. The starting address must
be an integer multiple of the block size defined
in the MPCS register. See Table 6-5 on page
6-14 for additional information.
R2 Bus Ready
Disable X When R2 is clear, bus ready must be active to
complete a bus cycle. When R2 is set, R1:0
control the number of bus wait states and bus
ready is ignored.
R1:0 Wait State
Value 3H R1:0 define the minimum number of wait states
inserted into the bus cycle.
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products. A starting address
other than an integer multiple of the block size defined in the MPCS register
causes unreliable chip-select operation. (See Table 6-5 on page 6-14 for details.)
Reading this register and the MPCS register (before writing them) enables the
MCS chip-selects; however, none of the programmable fields will be properly ini-
tialized.
15 0
R
1
R
0
R
2
U
1
3
U
1
5
U
1
4
U
1
7
U
1
6
U
1
9
U
1
8
A1143-0B