Intel 80C186XL, User Manual

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9-13
TIMER/COUNTER UNIT
The timer counting from its initial count (usually zero) to its maximum count (either Maxcount
Compare A or B) and resetting to zero defines one timing cycle. A Maxcount Compare value of
0 implies a maximum count of 65536, a Maxcount Compare value of 1 implies a maximum count
of 1, etc.
Only equivalence between the Timer Count and Maxcount Compare registers is checked. The
count does not reset to zero if its value is greater than the maximum count. If the count value ex-
ceeds the Maxcount Compare value, the timer counts to 0FFFFH, increments to zero, then counts
to the value in the Maxcount Compare register. Upon reaching a maximum count value, the Max-
imum Count (MC) bit in the Timer Control register sets. The MC bit must be cleared by writing
to the Timer Control register. This is not done automatically.
The Timer/Counter Unit can be configured to execute different counting sequences. The timers
can operate in single maximum count mode (all timers) or dual maximum count mode (Timers 0
and 1 only). They can also be programmed to run continuously in either of these modes. The Al-
ternate (ALT) bit in the Timer Control register determines the counting modes used by Timers 0
and 1.
All timers can use single maximum count mode, where only Maxcount Compare A is used. The
timer will count to the value contained in Maxcount Compare A and reset to zero. Timer 2 can
operate only in this mode.
Timers 0 and 1 can also use dual maximum count mode. In this mode, Maxcount Compare A and
Maxcount Compare B are both used. The timer counts to the value contained in Maxcount Com-
pare A, resets to zero, counts to the value contained in Maxcount Compare B, and resets to zero
again. The Register In Use (RIU) bit in the Timer Control register indicates which Maxcount
Compare register is currently in use.
The timers can be programmed to run continuously in single maximum count and dual maximum
count modes. The Continuous (CONT) bit in the Timer Control register determines whether a
timer is disabled after a single counting sequence.
9.2.3.1 Retriggering
The timer input pins affect timer counting in three ways (see Table 9-2). The programming of the
External (EXT) and Retrigger (RTG) bits in the Timer Control register determines how the input
signals are used. When the timers are clocked internally, the RTG bit determines whether the in-
put pin enables timer counting or retriggers the current timing cycle.
When the EXT and RTG bits are clear, the timer counts internal timer events. In this mode, the
input is level-sensitive, not edge-sensitive. A low-to-high transition on the timer input is not re-
quired for operation. The input pin acts as an external enable. If the input is high, the timer will
count through its sequence, provided the timer remains enabled.