C-7
INSTRUCTION SET DESCRIPTIONS
BOUND
Detect Value Out of Range:
BOUND
dest, src
Provides array bounds checking in
hardware. The calculated array index
is placed in one of the general purpose
registers, and the upper and lower
bounds of the array are placed in two
consecutive memory locations. The
contents of the register are compared
with the memory location values, and if
the register value is less than the first
location or greater than the second
memory location, a trap type 5 is
generated.
Instruction Operands:
BOUND reg, mem
if
((dest) < (src) or (dest) > ((src) + 2)
then
(SP)
←
(SP) – 2
((SP) + 1 : (SP))
←
FLAGS
(IF)
←
0
(TF)
←
0
(SP)
←
(SP) – 2
((SP) + 1 : (SP))
←
(CS)
(CS)
←
(1EH)
(SP)
←
(SP) – 2
((SP) + 1 : (SP))
←
(IP)
(IP)
←
(1CH)
AF –
CF –
DF –
IF –
OF –
PF –
SF –
TF –
ZF –
CALL
Call Procedure:
CALL procedure-name
Activates an out-of-line procedure,
saving information on the stack to
permit a RET (return) instruction in the
procedure to transfer control back to
the instruction following the CALL. The
assembler generates a different type
of CALL instruction depending on
whether the programmer has defined
the procedure name as NEAR or FAR.
Instruction Operands:
CALL near-proc
CALL far-proc
CALL memptr16
CALL regptr16
CALL memptr32
if
Inter-segment
then
(SP)
←
(SP) – 2
((SP) +1:(SP))
←
(CS)
(CS)
←
SEG
(SP)
←
(SP) – 2
((SP) +1:(SP))
←
(IP)
(IP)
←
dest
AF –
CF –
DF –
IF –
OF –
PF –
SF –
TF –
ZF –
Table C-4. Instruction Set (Continued)
Name
Description
Operation
Flags
Affected
NOTE:
The three symbols used in the Flags Affected column are defined as follows:
– the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
ü
the flag is updated after the instruction is executed
Summary of Contents for 80C186XL
Page 1: ...80C186XL 80C188XL Microprocessor User s Manual...
Page 2: ...80C186XL 80C188XL Microprocessor User s Manual 1995...
Page 18: ...1 Introduction...
Page 19: ......
Page 27: ......
Page 28: ...2 Overview of the 80C186 Family Architecture...
Page 29: ......
Page 79: ......
Page 80: ...3 Bus Interface Unit...
Page 81: ......
Page 127: ......
Page 128: ...4 Peripheral Control Block...
Page 129: ......
Page 137: ......
Page 138: ...5 ClockGenerationand Power Management...
Page 139: ......
Page 154: ...6 Chip Select Unit...
Page 155: ......
Page 178: ...7 Refresh Control Unit...
Page 179: ......
Page 193: ......
Page 194: ...8 Interrupt Control Unit...
Page 195: ......
Page 227: ......
Page 228: ...9 Timer Counter Unit...
Page 229: ......
Page 253: ......
Page 254: ...10 Direct Memory Access Unit...
Page 255: ......
Page 283: ......
Page 284: ...11 Math Coprocessing...
Page 285: ......
Page 302: ...12 ONCE Mode...
Page 303: ......
Page 306: ...A 80C186 Instruction Set Additions and Extensions...
Page 307: ......
Page 318: ...B Input Synchronization...
Page 319: ......
Page 322: ...C Instruction Set Descriptions...
Page 323: ......
Page 371: ......
Page 372: ...D Instruction Set Opcodes and Clock Cycles...
Page 373: ......
Page 396: ...Index...
Page 397: ......