INSTRUCTION SET DESCRIPTIONS
C-14
ENTER
Procedure Entry:
ENTER
locals, levels
Executes the calling sequence for a
high-level language. It saves the
current frame pointer in BP, copies the
frame pointers from procedures below
the current call (to allow access to
local variables in these procedures)
and allocates space on the stack for
the local variables of the current
procedure invocation.
Instruction Operands:
ENTER locals, level
(SP)
←
(SP) – 2
((SP) + 1:(SP))
←
(BP)
(FP)
←
(SP)
if
level > 0
then
repeat (level – 1) times
(BP)
←
(BP) – 2
(SP)
←
(SP) – 2
((SP) + 1:(SP))
←
(BP)
end repeat
(SP)
←
(SP) – 2
((SP) + 1:(SP))
←
(FP)
end if
(BP)
←
(FP)
(SP)
←
(SP) – (locals)
AF –
CF –
DF –
IF –
OF –
PF –
SF –
TF –
ZF –
ESC
Escape:
ESC
Provides a mechanism by which other
processors (coprocessors) may
receive their instructions from the 8086
or 8088 instruction stream and make
use of the 8086 or 8088 addressing
modes. The CPU (8086 or 8088) does
a no operation (NOP) for the ESC
instruction other than to access a
memory operand and place it on the
bus.
Instruction Operands:
ESC immed, mem
ESC immed, reg
if
mod
≠
11
then
data bus
←
(EA)
AF –
CF –
DF –
IF –
OF –
PF –
SF –
TF –
ZF –
Table C-4. Instruction Set (Continued)
Name
Description
Operation
Flags
Affected
NOTE:
The three symbols used in the Flags Affected column are defined as follows:
– the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
ü
the flag is updated after the instruction is executed
Summary of Contents for 80C186XL
Page 1: ...80C186XL 80C188XL Microprocessor User s Manual...
Page 2: ...80C186XL 80C188XL Microprocessor User s Manual 1995...
Page 18: ...1 Introduction...
Page 19: ......
Page 27: ......
Page 28: ...2 Overview of the 80C186 Family Architecture...
Page 29: ......
Page 79: ......
Page 80: ...3 Bus Interface Unit...
Page 81: ......
Page 127: ......
Page 128: ...4 Peripheral Control Block...
Page 129: ......
Page 137: ......
Page 138: ...5 ClockGenerationand Power Management...
Page 139: ......
Page 154: ...6 Chip Select Unit...
Page 155: ......
Page 178: ...7 Refresh Control Unit...
Page 179: ......
Page 193: ......
Page 194: ...8 Interrupt Control Unit...
Page 195: ......
Page 227: ......
Page 228: ...9 Timer Counter Unit...
Page 229: ......
Page 253: ......
Page 254: ...10 Direct Memory Access Unit...
Page 255: ......
Page 283: ......
Page 284: ...11 Math Coprocessing...
Page 285: ......
Page 302: ...12 ONCE Mode...
Page 303: ......
Page 306: ...A 80C186 Instruction Set Additions and Extensions...
Page 307: ......
Page 318: ...B Input Synchronization...
Page 319: ......
Page 322: ...C Instruction Set Descriptions...
Page 323: ......
Page 371: ......
Page 372: ...D Instruction Set Opcodes and Clock Cycles...
Page 373: ......
Page 396: ...Index...
Page 397: ......