11-7
MATH COPROCESSING
11.3.2 80C187 Data Types
The microprocessor/math coprocessor combination supports seven data types:
•
Word Integer — A signed 16-bit numeric value. All operations assume a 2’s complement
representation.
•
Short Integer — A signed 32-bit numeric value (double word). All operations assume a 2’s
complement representation.
•
Long Integer — A signed 64-bit numeric value (quad word). All operations assume a 2’s
complement representation.
•
Packed Decimal — A signed numeric value contained in an 80-bit BCD format.
•
Short Real — A signed 32-bit floating point numeric value.
•
Long Real — A signed 64-bit floating point numeric value.
•
Temporary Real — A signed 80-bit floating point numeric value. Temporary real is the
native 80C187 format.
Figure 11-1 graphically represents these data types.
11.4 MICROPROCESSOR AND COPROCESSOR OPERATION
The 80C187 interfaces directly to the microprocessor (as shown in Figure 11-2) and operates as
an I/O-mapped slave peripheral device. Hardware handshaking requires connections between the
80C187 and four special pins on the processor: NCS, BUSY, PEREQ and ERROR. These pins
are multiplexed with MCS3, TEST, MCS0, and MCS1, respectively. When the processor leaves
reset, the presence of the 80C187 automatically places the processor in Enhanced Mode and con-
figures the pins correctly. MCS2 retains its function as a chip-select and the processor retains the
wait state and ready programming for the entire mid-range memory block, even though MCS0,
MCS1 and MCS3 are no longer available.
Summary of Contents for 80C186XL
Page 1: ...80C186XL 80C188XL Microprocessor User s Manual...
Page 2: ...80C186XL 80C188XL Microprocessor User s Manual 1995...
Page 18: ...1 Introduction...
Page 19: ......
Page 27: ......
Page 28: ...2 Overview of the 80C186 Family Architecture...
Page 29: ......
Page 79: ......
Page 80: ...3 Bus Interface Unit...
Page 81: ......
Page 127: ......
Page 128: ...4 Peripheral Control Block...
Page 129: ......
Page 137: ......
Page 138: ...5 ClockGenerationand Power Management...
Page 139: ......
Page 154: ...6 Chip Select Unit...
Page 155: ......
Page 178: ...7 Refresh Control Unit...
Page 179: ......
Page 193: ......
Page 194: ...8 Interrupt Control Unit...
Page 195: ......
Page 227: ......
Page 228: ...9 Timer Counter Unit...
Page 229: ......
Page 253: ......
Page 254: ...10 Direct Memory Access Unit...
Page 255: ......
Page 283: ......
Page 284: ...11 Math Coprocessing...
Page 285: ......
Page 302: ...12 ONCE Mode...
Page 303: ......
Page 306: ...A 80C186 Instruction Set Additions and Extensions...
Page 307: ......
Page 318: ...B Input Synchronization...
Page 319: ......
Page 322: ...C Instruction Set Descriptions...
Page 323: ......
Page 371: ......
Page 372: ...D Instruction Set Opcodes and Clock Cycles...
Page 373: ......
Page 396: ...Index...
Page 397: ......