INSTRUCTION SET DESCRIPTIONS
C-26
LDS
Load Pointer Using DS:
LDS
dest, src
Transfers a 32-bit pointer variable from
the source operand, which must be a
memory operand, to the destination
operand and register DS. The offset
word of the pointer is transferred to the
destination operand, which may be
any 16-bit general register. The
segment word of the pointer is
transferred to register DS.
Instruction Operands:
LDS reg16, mem32
(dest)
←
(EA)
(DS)
←
(EA + 2)
AF –
CF –
DF –
IF –
OF –
PF –
SF –
TF –
ZF –
LEA
Load Effective Address:
LEA dest, src
Transfers the offset of the source
operand (rather than its value) to the
destination operand.
Instruction Operands:
LEA reg16, mem16
(dest)
←
EA
AF –
CF –
DF –
IF –
OF –
PF –
SF –
TF –
ZF –
LEAVE
Leave:
LEAVE
Reverses the action of the most recent
ENTER instruction. Collapses the last
stack frame created. First, LEAVE
copies the current BP to the stack
pointer releasing the stack space
allocated to the current procedure.
Second, LEAVE pops the old value of
BP from the stack, to return to the
calling procedure's stack frame. A
return (RET) instruction will remove
arguments stacked by the calling
procedure for use by the called
procedure.
Instruction Operands:
none
(SP)
←
(BP)
(BP)
←
((SP) + 1:(SP))
(SP)
←
(SP) + 2
AF –
CF –
DF –
IF –
OF –
PF –
SF –
TF –
ZF –
Table C-4. Instruction Set (Continued)
Name
Description
Operation
Flags
Affected
NOTE:
The three symbols used in the Flags Affected column are defined as follows:
– the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
ü
the flag is updated after the instruction is executed
Summary of Contents for 80C186XL
Page 1: ...80C186XL 80C188XL Microprocessor User s Manual...
Page 2: ...80C186XL 80C188XL Microprocessor User s Manual 1995...
Page 18: ...1 Introduction...
Page 19: ......
Page 27: ......
Page 28: ...2 Overview of the 80C186 Family Architecture...
Page 29: ......
Page 79: ......
Page 80: ...3 Bus Interface Unit...
Page 81: ......
Page 127: ......
Page 128: ...4 Peripheral Control Block...
Page 129: ......
Page 137: ......
Page 138: ...5 ClockGenerationand Power Management...
Page 139: ......
Page 154: ...6 Chip Select Unit...
Page 155: ......
Page 178: ...7 Refresh Control Unit...
Page 179: ......
Page 193: ......
Page 194: ...8 Interrupt Control Unit...
Page 195: ......
Page 227: ......
Page 228: ...9 Timer Counter Unit...
Page 229: ......
Page 253: ......
Page 254: ...10 Direct Memory Access Unit...
Page 255: ......
Page 283: ......
Page 284: ...11 Math Coprocessing...
Page 285: ......
Page 302: ...12 ONCE Mode...
Page 303: ......
Page 306: ...A 80C186 Instruction Set Additions and Extensions...
Page 307: ......
Page 318: ...B Input Synchronization...
Page 319: ......
Page 322: ...C Instruction Set Descriptions...
Page 323: ......
Page 371: ......
Page 372: ...D Instruction Set Opcodes and Clock Cycles...
Page 373: ......
Page 396: ...Index...
Page 397: ......