Intel 80C186XL, User Manual

Page: 211 / 405

INTERRUPT CONTROL UNIT
8-16
8.4.2 Interrupt Request Register
The Interrupt Request register (Figure 8-7) has one bit for each interrupt source. When a source
requests an interrupt, its Interrupt Request bit is set (without regard to whether the interrupt is
masked). The Interrupt Request bit is cleared when the interrupt is acknowledged. An external
interrupt pin must remain asserted until its interrupt is acknowledged. Otherwise, the Interrupt
Request bit will be cleared, but the interrupt will not be serviced.
Figure 8-7. Interrupt Request Register
8.4.3 Interrupt Mask Register
The Interrupt Mask register (Figure 8-8) contains a mask bit for each interrupt source. This reg-
ister allows you to mask (disable) individual interrupts. Set a mask bit to disable interrupts from
the corresponding source. The mask bit is the same as the one in the Interrupt Control register.
Modifying a bit in either register also modifies that same bit in the other register.
Register Name: Interrupt Request Register
Register Mnemonic: REQST
Register Function: Stores pending interrupt requests
Bit
Mnemonic
Bit Name
Reset
State
Function
INT3:0 External
Interrupts 0000 0 A bit is set to indicate a pending interrupt from
the corresponding external interrupt pin.
DMA1:0 DMA
Interrupt 0 A bit is set to indicate a pending interrupt from
the corresponding DMA channel.
TMR Timer
Interrupt 0 This bit is set to indicate a pending interrupt
from one of the timers.
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.
A1201-A0
15 0
T
M
R
D
M
A
0
D
M
A
1
I
N
T
0
I
N
T
1
I
N
T
2
I
N
T
3