INSTRUCTION SET OPCODES AND CLOCK CYCLES
D-6
BIT MANIPULATION INSTRUCTIONS (Continued)
TEST= And function to flags, no result
register/memory and register
1 0 0 0 0 1 0 w
mod reg r/m
3/10
immediate data and register/memory
1 1 1 1 0 1 1 w
mod 000 r/m
data
data if w=1
4/10
immediate data and accumulator
1 0 1 0 1 0 0 w
data
data if w=1
3/4
(1)
Shifts/Rotates
register/memory by 1
1 1 0 1 0 0 0 w
mod TTT r/m
2/15
register/memory by CL
1 1 0 1 0 0 1 w
mod TTT r/m
5+n/17+n
register/memory by Count
1 1 0 0 0 0 0 w
mod TTT r/m
count
5+n/17+n
STRING MANIPULATION INSTRUCTIONS
MOVS = Move byte/word
1 0 1 0 0 1 0 w
14
INS = Input byte/word from DX port
0 1 1 0 1 1 0 w
14
OUTS = Output byte/word to DX port
0 1 1 0 1 1 1 w
14
CMPS = Compare byte/word
1 0 1 0 0 1 1 w
22
SCAS = Scan byte/word
1 0 1 0 1 1 1 w
15
STRING MANIPULATION INSTRUCTIONS (Continued)
LODS = Load byte/word to AL/AX
1 0 1 0 1 1 0 w
12
STOS = Store byte/word from AL/AX
1 0 1 0 1 0 1 w
10
Repeated by count in CX:
MOVS = Move byte/word
1 1 1 1 0 0 1 0
1 0 1 0 0 1 0 w
8+8n
INS = Input byte/word from DX port
1 1 1 1 0 0 1 0
0 1 1 0 1 1 0 w
8-8n
OUTS = Output byte/word to DX port
1 1 1 1 0 0 1 0
0 1 1 0 1 1 1 w
8+8n
CMPS = Compare byte/word
1 1 1 1 0 0 1 z
1 0 1 0 0 1 1 w
5+22n
SCAS = Scan byte/word
1 1 1 1 0 0 1 z
1 0 1 0 1 1 1 w
5+15n
LODS = Load byte/word to AL/AX
1 1 1 1 0 0 1 0
0 1 0 1 0 0 1 w
6+11n
STOS = Store byte/word from AL/AX
1 1 1 1 0 1 0 0
0 1 0 1 0 0 1 w
6+9n
Table D-2. Instruction Set Summary (Continued)
Function
Format
Clocks
Notes
NOTES:
1.
Clock cycles are given for 8-bit/16-bit operations.
2.
Clock cycles are given for jump not taken/jump taken.
3.
Clock cycles are given for interrupt taken/interrupt not taken.
4.
If TEST = 0
Shading indicates additions and enhancements to the 8086/8088 instruction set. See Appendix A, “80C186
Instruction Set Additions and Extensions,” for details.
Summary of Contents for 80C186XL
Page 1: ...80C186XL 80C188XL Microprocessor User s Manual...
Page 2: ...80C186XL 80C188XL Microprocessor User s Manual 1995...
Page 18: ...1 Introduction...
Page 19: ......
Page 27: ......
Page 28: ...2 Overview of the 80C186 Family Architecture...
Page 29: ......
Page 79: ......
Page 80: ...3 Bus Interface Unit...
Page 81: ......
Page 127: ......
Page 128: ...4 Peripheral Control Block...
Page 129: ......
Page 137: ......
Page 138: ...5 ClockGenerationand Power Management...
Page 139: ......
Page 154: ...6 Chip Select Unit...
Page 155: ......
Page 178: ...7 Refresh Control Unit...
Page 179: ......
Page 193: ......
Page 194: ...8 Interrupt Control Unit...
Page 195: ......
Page 227: ......
Page 228: ...9 Timer Counter Unit...
Page 229: ......
Page 253: ......
Page 254: ...10 Direct Memory Access Unit...
Page 255: ......
Page 283: ......
Page 284: ...11 Math Coprocessing...
Page 285: ......
Page 302: ...12 ONCE Mode...
Page 303: ......
Page 306: ...A 80C186 Instruction Set Additions and Extensions...
Page 307: ......
Page 318: ...B Input Synchronization...
Page 319: ......
Page 322: ...C Instruction Set Descriptions...
Page 323: ......
Page 371: ......
Page 372: ...D Instruction Set Opcodes and Clock Cycles...
Page 373: ......
Page 396: ...Index...
Page 397: ......