INSTRUCTION SET DESCRIPTIONS
C-40
SHL
SAL
Shift Logical Left:
Shift Arithmetic Left:
SHL
dest, count
SAL
dest, count
Shifts the destination byte or word left
by the number of bits specified in the
count operand. Zeros are shifted in on
the right. If the sign bit retains its
original value, then OF is cleared.
Instruction Operands:
SHL reg, n
SAL reg, n
SHL mem, n
SAL mem, n
SHL reg, CL
SAL reg, CL
SHL mem, CL
SAL mem, CL
(temp)
←
count
do while (temp)
≠
0
(CF)
←
high-order bit of (dest)
(dest)
←
(dest) × 2
(temp)
←
(temp) – 1
if
count = 1
then
if
high-order bit of (dest)
≠
(CE)
then
(OF)
←
1
else
(OF)
←
0
else
(OF) undefined
AF ?
CF
ü
DF –
IF –
OF
ü
PF
ü
SF
ü
TF –
ZF
ü
SAR
Shift Arithmetic Right:
SAR dest, count
Shifts the bits in the destination
operand (byte or word) to the right by
the number of bits specified in the
count operand. Bits equal to the
original high-order (sign) bit are shifted
in on the left, preserving the sign of the
original value. Note that SAR does not
produce the same result as the
dividend of an "equivalent" IDIV
instruction if the destination operand is
negative and 1 bits are shifted out. For
example, shifting –5 right by one bit
yields –3, while integer division –5 by 2
yields –2. The difference in the instruc-
tions is that IDIV truncates all numbers
toward zero, while SAR truncates
positive numbers toward zero and
negative numbers toward negative
infinity.
Instruction Operands:
SAR reg, n
SAR mem, n
SAR reg, CL
SAR mem, CL
(temp)
←
count
do while (temp)
≠
0
(CF)
←
low-order bit of (dest)
(dest)
←
(dest) / 2
(temp)
←
(temp) – 1
if
count = 1
then
if
high-order bit of (dest)
≠
next-to-high-order bit of (dest)
then
(OF)
←
1
else
(OF)
←
0
else
(OF)
←
0
AF ?
CF
ü
DF –
IF –
OF
ü
PF
ü
SF
ü
TF –
ZF
ü
Table C-4. Instruction Set (Continued)
Name
Description
Operation
Flags
Affected
NOTE:
The three symbols used in the Flags Affected column are defined as follows:
– the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
ü
the flag is updated after the instruction is executed
Summary of Contents for 80C186XL
Page 1: ...80C186XL 80C188XL Microprocessor User s Manual...
Page 2: ...80C186XL 80C188XL Microprocessor User s Manual 1995...
Page 18: ...1 Introduction...
Page 19: ......
Page 27: ......
Page 28: ...2 Overview of the 80C186 Family Architecture...
Page 29: ......
Page 79: ......
Page 80: ...3 Bus Interface Unit...
Page 81: ......
Page 127: ......
Page 128: ...4 Peripheral Control Block...
Page 129: ......
Page 137: ......
Page 138: ...5 ClockGenerationand Power Management...
Page 139: ......
Page 154: ...6 Chip Select Unit...
Page 155: ......
Page 178: ...7 Refresh Control Unit...
Page 179: ......
Page 193: ......
Page 194: ...8 Interrupt Control Unit...
Page 195: ......
Page 227: ......
Page 228: ...9 Timer Counter Unit...
Page 229: ......
Page 253: ......
Page 254: ...10 Direct Memory Access Unit...
Page 255: ......
Page 283: ......
Page 284: ...11 Math Coprocessing...
Page 285: ......
Page 302: ...12 ONCE Mode...
Page 303: ......
Page 306: ...A 80C186 Instruction Set Additions and Extensions...
Page 307: ......
Page 318: ...B Input Synchronization...
Page 319: ......
Page 322: ...C Instruction Set Descriptions...
Page 323: ......
Page 371: ......
Page 372: ...D Instruction Set Opcodes and Clock Cycles...
Page 373: ......
Page 396: ...Index...
Page 397: ......