A-3
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS
Figure A-1. Formal Definition of ENTER
ENTER treats a reentrant procedure as a procedure calling another procedure at the same lexical
level. A reentrant procedure can address only its own variables and variables of higher-level call-
ing procedures. ENTER ensures this by copying only stack frame pointers from higher-level pro-
cedures.
Block-structured high-level languages use lexical nesting levels to control access to variables of
previously nested procedures. For example, assume for Figure A-2 that Procedure A calls Proce-
dure B, which calls Procedure C, which calls Procedure D. Procedure C will have access to the
variables of Main and Procedure A, but not to those of Procedure B because Procedures C and B
operate at the same lexical nesting level.
The following is a summary of the variable access for Figure A-2.
1.
Main has variables at fixed locations.
2.
Procedure A can access only the fixed variables of Main.
3.
Procedure B can access only the variables of Procedure A and Main.
Procedure B cannot access the variables of Procedure C or Procedure D.
4.
Procedure C can access only the variables of Procedure A and Main.
Procedure C cannot access the variables of Procedure B or Procedure D.
5.
Procedure D can access the variables of Procedure C, Procedure A and Main.
Procedure D cannot access the variables of Procedure B.
The following listing gives the formal definition of the
ENTER instruction for all cases.
LEVEL denotes the value of the second operand.
Push BP
Set a temporary value FRAME_PTR: = SP
If LEVEL > 0 then
Repeat (LEVEL - 1) times:
BP:=BP - 2
Push the word pointed to by BP
End Repeat
Push FRAME_PTR
End if
BP:=FRAME_PTR
SP:=SP - first operand
Summary of Contents for 80C186XL
Page 1: ...80C186XL 80C188XL Microprocessor User s Manual...
Page 2: ...80C186XL 80C188XL Microprocessor User s Manual 1995...
Page 18: ...1 Introduction...
Page 19: ......
Page 27: ......
Page 28: ...2 Overview of the 80C186 Family Architecture...
Page 29: ......
Page 79: ......
Page 80: ...3 Bus Interface Unit...
Page 81: ......
Page 127: ......
Page 128: ...4 Peripheral Control Block...
Page 129: ......
Page 137: ......
Page 138: ...5 ClockGenerationand Power Management...
Page 139: ......
Page 154: ...6 Chip Select Unit...
Page 155: ......
Page 178: ...7 Refresh Control Unit...
Page 179: ......
Page 193: ......
Page 194: ...8 Interrupt Control Unit...
Page 195: ......
Page 227: ......
Page 228: ...9 Timer Counter Unit...
Page 229: ......
Page 253: ......
Page 254: ...10 Direct Memory Access Unit...
Page 255: ......
Page 283: ......
Page 284: ...11 Math Coprocessing...
Page 285: ......
Page 302: ...12 ONCE Mode...
Page 303: ......
Page 306: ...A 80C186 Instruction Set Additions and Extensions...
Page 307: ......
Page 318: ...B Input Synchronization...
Page 319: ......
Page 322: ...C Instruction Set Descriptions...
Page 323: ......
Page 371: ......
Page 372: ...D Instruction Set Opcodes and Clock Cycles...
Page 373: ......
Page 396: ...Index...
Page 397: ......