INSTRUCTION SET DESCRIPTIONS
C-20
INTO
Interrupt on Overflow:
INTO
Generates a software interrupt if the
overflow flag (OF) is set; otherwise
control proceeds to the following
instruction without activating an
interrupt procedure. INTO addresses
the target interrupt procedure (its type
is 4) through the interrupt pointer at
location 10H; it clears the TF and IF
flags and otherwise operates like INT.
INTO may be written following an
arithmetic or logical operation to
activate an interrupt procedure if
overflow occurs.
Instruction Operands:
none
if
(OF) = 1
then
(SP)
←
(SP) – 2
((SP) + 1:(SP))
←
FLAGS
(IF)
←
0
(TF)
←
0
(SP)
←
(SP) – 2
((SP) + 1:(SP))
←
(CS)
(CS)
←
(12H)
(SP)
←
(SP) – 2
((SP) + 1:(SP))
←
(IP)
(IP)
←
(10H)
AF –
CF –
DF –
IF –
OF –
PF –
SF –
TF –
ZF –
IRET
Interrupt Return:
IRET
Transfers control back to the point of
interruption by popping IP, CS, and the
flags from the stack. IRET thus affects
all flags by restoring them to previously
saved values. IRET is used to exit any
interrupt procedure, whether activated
by hardware or software.
Instruction Operands:
none
(IP)
←
((SP) + 1:(SP))
(SP)
←
(SP) + 2
(CS)
←
((SP) + 1:(SP))
(SP)
←
(SP) + 2
FLAGS
←
((SP) + 1:(SP))
(SP)
←
(SP) + 2
AF
ü
CF
ü
DF
ü
IF
ü
OF
ü
PF
ü
SF
ü
TF
ü
ZF
ü
JA
JNBE
Jump on Above:
Jump on Not Below or Equal:
JA disp8
JNBE
disp8
Transfers control to the target location
if the tested condition ((CF=0) or
(ZF=0)) is true.
Instruction Operands:
JA short-label
JNBE short-label
if
((CF) = 0) or ((ZF) = 0)
then
(IP)
←
(IP) + disp8 (sign-ext to 16 bits)
AF –
CF –
DF –
IF –
OF –
PF –
SF –
TF –
ZF –
Table C-4. Instruction Set (Continued)
Name
Description
Operation
Flags
Affected
NOTE:
The three symbols used in the Flags Affected column are defined as follows:
– the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
ü
the flag is updated after the instruction is executed
Summary of Contents for 80C186XL
Page 1: ...80C186XL 80C188XL Microprocessor User s Manual...
Page 2: ...80C186XL 80C188XL Microprocessor User s Manual 1995...
Page 18: ...1 Introduction...
Page 19: ......
Page 27: ......
Page 28: ...2 Overview of the 80C186 Family Architecture...
Page 29: ......
Page 79: ......
Page 80: ...3 Bus Interface Unit...
Page 81: ......
Page 127: ......
Page 128: ...4 Peripheral Control Block...
Page 129: ......
Page 137: ......
Page 138: ...5 ClockGenerationand Power Management...
Page 139: ......
Page 154: ...6 Chip Select Unit...
Page 155: ......
Page 178: ...7 Refresh Control Unit...
Page 179: ......
Page 193: ......
Page 194: ...8 Interrupt Control Unit...
Page 195: ......
Page 227: ......
Page 228: ...9 Timer Counter Unit...
Page 229: ......
Page 253: ......
Page 254: ...10 Direct Memory Access Unit...
Page 255: ......
Page 283: ......
Page 284: ...11 Math Coprocessing...
Page 285: ......
Page 302: ...12 ONCE Mode...
Page 303: ......
Page 306: ...A 80C186 Instruction Set Additions and Extensions...
Page 307: ......
Page 318: ...B Input Synchronization...
Page 319: ......
Page 322: ...C Instruction Set Descriptions...
Page 323: ......
Page 371: ......
Page 372: ...D Instruction Set Opcodes and Clock Cycles...
Page 373: ......
Page 396: ...Index...
Page 397: ......