INSTRUCTION SET DESCRIPTIONS
C-16
IDIV
Integer Divide:
IDIV
src
Performs a signed division of the
accumulator (and its extension) by the
source operand. If the source operand
is a byte, it is divided into the double-
length dividend assumed to be in
registers AL and AH; the single-length
quotient is returned in AL, and the
single-length remainder is returned in
AH. For byte integer division, the
maximum positive quotient is +127
(7FH) and the minimum negative
quotient is –127 (81H).
If the source operand is a word, it is
divided into the double-length dividend
in registers AX and DX; the single-
length quotient is returned in AX, and
the single-length remainder is returned
in DX. For word integer division, the
maximum positive quotient is +32,767
(7FFFH) and the minimum negative
quotient is –32,767 (8001H).
If the quotient is positive and exceeds
the maximum, or is negative and is
less than the minimum, the quotient
and remainder are undefined, and a
type 0 interrupt is generated. In
particular, this occurs if division by 0 is
attempted. Nonintegral quotients are
truncated (toward 0) to integers, and
the remainder has the same sign as
the dividend.
Instruction Operands:
IDIV reg
IDIV mem
When Source Operand is a Byte:
(temp)
←
(byte-src)
if
(temp) / (AX) > 0 and
(temp) / (AX) > 7FH or
(temp) / (AX) < 0 and
(temp) / (AX) < 0 – 7FH – 1
then (type 0 interrupt is generated)
(SP)
←
(SP) – 2
((SP) + 1:(SP))
←
FLAGS
(IF)
←
0
(TF)
←
0
(SP)
←
(SP) – 2
((SP) + 1:(SP))
←
(CS)
(CS)
←
(2)
(SP)
←
(SP) – 2
((SP) + 1:(SP))
←
(IP)
(IP)
←
(0)
else
(AL)
←
(temp) / (AX)
(AH)
←
(temp) % (AX)
When Source Operand is a Word:
(temp)
←
(word-src)
if
(temp) / (DX:AX) > 0 and
(temp) / (DX:AX) > 7FFFH or
(temp) / (DX:AX) < 0 and
(temp) / (DX:AX) < 0 – 7FFFH – 1
then (type 0 interrupt is generated)
(SP)
←
(SP) – 2
((SP) + 1:(SP))
←
FLAGS
(IF)
←
0
(TF)
←
0
(SP)
←
(SP) – 2
((SP) + 1:(SP))
←
(CS)
(CS)
←
(2)
(SP)
←
(SP) – 2
((SP) + 1:(SP))
←
(IP)
(IP)
←
(0)
else
(AX)
←
(temp) / (DX:AX)
(DX)
←
(temp) % (DX:AX)
AF ?
CF ?
DF –
IF –
OF ?
PF ?
SF ?
TF –
ZF ?
Table C-4. Instruction Set (Continued)
Name
Description
Operation
Flags
Affected
NOTE:
The three symbols used in the Flags Affected column are defined as follows:
– the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
ü
the flag is updated after the instruction is executed
Summary of Contents for 80C186XL
Page 1: ...80C186XL 80C188XL Microprocessor User s Manual...
Page 2: ...80C186XL 80C188XL Microprocessor User s Manual 1995...
Page 18: ...1 Introduction...
Page 19: ......
Page 27: ......
Page 28: ...2 Overview of the 80C186 Family Architecture...
Page 29: ......
Page 79: ......
Page 80: ...3 Bus Interface Unit...
Page 81: ......
Page 127: ......
Page 128: ...4 Peripheral Control Block...
Page 129: ......
Page 137: ......
Page 138: ...5 ClockGenerationand Power Management...
Page 139: ......
Page 154: ...6 Chip Select Unit...
Page 155: ......
Page 178: ...7 Refresh Control Unit...
Page 179: ......
Page 193: ......
Page 194: ...8 Interrupt Control Unit...
Page 195: ......
Page 227: ......
Page 228: ...9 Timer Counter Unit...
Page 229: ......
Page 253: ......
Page 254: ...10 Direct Memory Access Unit...
Page 255: ......
Page 283: ......
Page 284: ...11 Math Coprocessing...
Page 285: ......
Page 302: ...12 ONCE Mode...
Page 303: ......
Page 306: ...A 80C186 Instruction Set Additions and Extensions...
Page 307: ......
Page 318: ...B Input Synchronization...
Page 319: ......
Page 322: ...C Instruction Set Descriptions...
Page 323: ......
Page 371: ......
Page 372: ...D Instruction Set Opcodes and Clock Cycles...
Page 373: ......
Page 396: ...Index...
Page 397: ......