6-15
CHIP-SELECT UNIT
6.4.2.4
PCS Active Range
Each PCS chip-select starts at an offset above the base address programmed in the PACS register
and is active for 128 bytes. The base address can start on any 1 Kbyte memory or I/O address
location. Table 6-6 lists the active range for each PCS chip-select.
6.4.3
Bus Wait State and Ready Control
Normally, the bus ready input must be inactive at the appropriate time to insert wait states into
the bus cycle. The Chip-Select Unit can ignore the state of the bus ready input to extend and com-
plete the bus cycle automatically. Most memory and peripheral devices operate properly using
three or fewer wait states. However, accessing such devices as a dual-port memory, an expansion
bus interface, a system bus interface or remote peripheral devices can require more than three
wait states to complete a bus cycle.
A three-bit field (R2:0) in the control registers defines the number of wait states and the ready
requirements for the chip-selects. Figure 6-11 shows a simplified logic diagram of the wait state
and ready control functions.
Table 6-6. PCS Active Range
Chip-
Select
Active Range
Start Address
Ending Address
PCS0
Base
Base + 127 (7FH)
PCS1
Base + 128 (080H)
Base + 255 (0FFH)
PCS2
Base + 256 (100H)
Base + 383 (17FH)
PCS3
Base + 384 (180H)
Base + 511 (1FFH)
PCS4
Base + 512 (200H)
Base + 639 (27FH)
PCS5
Base + 640 (280H)
Base + 767 (2FFH)
PCS6
Base + 768 (300H)
Base + 895 (37FH)
Summary of Contents for 80C186XL
Page 1: ...80C186XL 80C188XL Microprocessor User s Manual...
Page 2: ...80C186XL 80C188XL Microprocessor User s Manual 1995...
Page 18: ...1 Introduction...
Page 19: ......
Page 27: ......
Page 28: ...2 Overview of the 80C186 Family Architecture...
Page 29: ......
Page 79: ......
Page 80: ...3 Bus Interface Unit...
Page 81: ......
Page 127: ......
Page 128: ...4 Peripheral Control Block...
Page 129: ......
Page 137: ......
Page 138: ...5 ClockGenerationand Power Management...
Page 139: ......
Page 154: ...6 Chip Select Unit...
Page 155: ......
Page 178: ...7 Refresh Control Unit...
Page 179: ......
Page 193: ......
Page 194: ...8 Interrupt Control Unit...
Page 195: ......
Page 227: ......
Page 228: ...9 Timer Counter Unit...
Page 229: ......
Page 253: ......
Page 254: ...10 Direct Memory Access Unit...
Page 255: ......
Page 283: ......
Page 284: ...11 Math Coprocessing...
Page 285: ......
Page 302: ...12 ONCE Mode...
Page 303: ......
Page 306: ...A 80C186 Instruction Set Additions and Extensions...
Page 307: ......
Page 318: ...B Input Synchronization...
Page 319: ......
Page 322: ...C Instruction Set Descriptions...
Page 323: ......
Page 371: ......
Page 372: ...D Instruction Set Opcodes and Clock Cycles...
Page 373: ......
Page 396: ...Index...
Page 397: ......