Intel 80C186XL, User Manual

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OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2-46
2.3.4 Interrupt Response Time
Interrupt response time is the time from the CPU recognizing an interrupt until the first instruction
in the service routine is executed. Interrupt response time is less for interrupts or exceptions
which supply their own vector type. The maskable interrupt has a longer response time because
the vector type must be supplied by the Interrupt Control Unit (see Chapter 8, “Interrupt Control
Unit”).
Figure 2-27 shows the events that dictate interrupt response time for the interrupts that supply
their type. Note that an on-chip bus master, such as the DRAM Refresh Unit, can make use of
idle bus cycles. This can increase interrupt response time.
Figure 2-27. Interrupt Response Factors
2.3.5 Interrupt and Exception Priority
Interrupts can be recognized only on valid instruction boundaries. If an NMI and a maskable in-
terrupt are both recognized on the same instruction boundary, NMI has precedence. The
maskable interrupt will not be recognized until the Interrupt Enable bit is set and it is the highest
priority.
Clocks
Idle
Idle
Read CS
Idle
Push Flags
Idle
Push CS
Push IP
Idle
5
4
4
4
4
3
4
4
5
5
Read IP
Total 42
First Instruction Fetch
From Interrupt Routine
A1030-0A