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INTERRUPT CONTROL UNIT

8-10

8.3.6

Edge and Level Triggering

The external interrupts (INT3:0) can be programmed for either edge or level triggering (see “In-
terrupt Control Registers” on page 8-12). Both types of triggering are active high. An edge-trig-
gered interrupt is generated by a zero-to-one transition on an external interrupt pin. The pin must
remain high until after the CPU acknowledges the interrupt, then must go low to reset the edge-
detection circuitry. (See the current data sheet for timing requirements.) The edge-detection cir-
cuitry must be reset to enable further interrupts to occur.

A level-triggered interrupt is generated by a valid logic one on the external interrupt pin. The pin
must remain high until after the CPU acknowledges the interrupt. Unlike edge-triggered inter-
rupts, level-triggered interrupts will continue to occur if the pin remains high. A level-triggered
external interrupt pin must go low before the EOI command to prevent another interrupt.

NOTE

When external 8259As are cascaded into the Interrupt Control Unit, INT0 and
INT1 must be programmed for level-triggered interrupts.

8.3.7

Additional Latency and Response Time

The Interrupt Control Unit adds 5 clocks to the interrupt latency of the CPU. Cascade mode adds
13 clocks to the interrupt response time because the CPU must run the interrupt acknowledge bus
cycles. (See Figure 8-3 on page 8-11 and Figure 2-27 on page 2-46.)

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Summary of Contents for 80C186XL

Page 1: ...80C186XL 80C188XL Microprocessor User s Manual...

Page 2: ...80C186XL 80C188XL Microprocessor User s Manual 1995...

Page 3: ...s the right to make changes to these specifications at any time without notice Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product...

Page 4: ...2 1 4 Segment Registers 2 5 2 1 5 Instruction Pointer 2 6 2 1 6 Flags 2 7 2 1 7 Memory Segmentation 2 8 2 1 8 Logical Addresses 2 10 2 1 9 Dynamically Relocatable Code 2 13 2 1 10 Stack Implementatio...

Page 5: ...3 4 BUS CYCLE OPERATION 3 7 3 4 1 Address Status Phase 3 10 3 4 2 Data Phase 3 13 3 4 3 Wait States 3 13 3 4 4 Idle States 3 18 3 5 BUS CYCLES 3 20 3 5 1 Read Bus Cycles 3 20 3 5 1 1 Refresh Bus Cycl...

Page 6: ...1 1 1 Oscillator Operation 5 2 5 1 1 2 Selecting Crystals 5 5 5 1 2 Using an External Oscillator 5 6 5 1 3 Output from the Clock Generator 5 6 5 1 4 Reset and Clock Synchronization 5 6 5 2 POWER MANAG...

Page 7: ...dress Register 7 8 7 7 2 2 Refresh Clock Interval Register 7 8 7 7 2 3 Refresh Control Register 7 9 7 7 3 Programming Example 7 10 7 8 REFRESH OPERATION AND BUS HOLD 7 12 CHAPTER 8 INTERRUPT CONTROL U...

Page 8: ...0 CHAPTER 9 TIMER COUNTER UNIT 9 1 FUNCTIONAL OVERVIEW 9 1 9 2 PROGRAMMING THE TIMER COUNTER UNIT 9 6 9 2 1 Initialization Sequence 9 11 9 2 2 Clock Sources 9 12 9 2 3 Counting Modes 9 12 9 2 3 1 Retr...

Page 9: ...ers 10 10 10 2 1 2 Selecting Byte or Word Size Transfers 10 14 10 2 1 3 Selecting the Source of DMA Requests 10 17 10 2 1 4 Arming the DMA Channel 10 18 10 2 1 5 Selecting Channel Synchronization 10 1...

Page 10: ...RING LEAVING ONCE MODE 12 1 APPENDIX A 80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS A 1 80C186 INSTRUCTION SET ADDITIONS A 1 A 1 1 Data Transfer Instructions A 1 A 1 2 String Instructions A 2 A 1 3...

Page 11: ...sed Index Addressing 2 35 2 21 String Operand 2 36 2 22 I O Port Addressing 2 36 2 23 80C186 Modular Core Family Supported Data Types 2 38 2 24 Interrupt Control Unit 2 39 2 25 Interrupt Vector Table...

Page 12: ...2 Qualifying DEN with Chip Selects 3 36 3 33 Queue Status Timing 3 39 3 34 Timing Sequence Entering HOLD 3 40 3 35 Refresh Request During HOLD 3 42 3 36 Latching HLDA 3 43 3 37 Exiting HOLD 3 44 4 1 P...

Page 13: ...trol Register for Cascadable Interrupt Pins 8 15 8 7 Interrupt Request Register 8 16 8 8 Interrupt Mask Register 8 17 8 9 Priority Mask Register 8 18 8 10 In Service Register 8 19 8 11 Poll Register 8...

Page 14: ...ansfer Count Register 10 19 11 1 80C187 Supported Data Types 11 8 11 2 80C186 Modular Core Family 80C187 System Configuration 11 9 11 3 80C187 Configuration with a Partially Buffered Bus 11 12 11 4 80...

Page 15: ...eue Status Signal Decoding 3 38 3 8 Signal Condition Entering HOLD 3 40 4 1 Peripheral Control Block 4 3 5 1 Suggested Values for Inductor L1 in Third Overtone Oscillator Circuit 5 4 6 1 Chip Select U...

Page 16: ...nstruction Operands C 2 C 3 Flag Bit Functions C 3 C 4 Instruction Set C 4 D 1 Operand Variables D 1 D 2 Instruction Set Summary D 2 D 3 Machine Instruction Decoding Guide D 9 D 4 Mnemonic Encoding Ma...

Page 17: ...Unit 7 11 8 1 Initializing the Interrupt Control Unit for Master Mode 8 31 9 1 Configuring a Real Time Clock 9 18 9 2 Configuring a Square Wave Generator 9 21 9 3 Configuring a Digital One Shot 9 22 1...

Page 18: ...1 Introduction...

Page 19: ......

Page 20: ...run at twice the clock rate of the NMOS 80186 while consuming less than one fourth the power The 80186 family took another major step in 1990 with the introduction of the 80C186EB family The 80C186EB...

Page 21: ...EB C188EB 80C186EC C188EC and 80C186XL C188XL 80C186 Modular Core Without the word family this phrase refers only to the 16 bit bus mem bers of the 80C186 Modular Core Family 80C188 Modular Core This...

Page 22: ...able 1 2 Related Documents and Software Document Software Title Document Order No Embedded Microprocessors includes 186 family data sheets 272396 186 Embedded Microprocessor Line Card 272079 80186 801...

Page 23: ...number and respond to the system prompts After you select a doc ument the system sends a copy to your fax machine Each document has an order number and is listed in a subject catalog The first time yo...

Page 24: ...Europe The toll free BBS available in the U S and Canada offers lists of documents available from FaxBack a master list of files available from the application BBS and a BBS user s guide The BBS file...

Page 25: ...les 1 and 6 or 3 7 for files 3 4 5 6 and 7 and press Enter The BBS displays the approx imate time required to download the selected files and gives you the option to download them 1 3 3 CompuServe For...

Page 26: ...U S and Canada 708 296 9333 U S from overseas 44 0 1793 431155 Europe U K 44 0 1793 421333 Germany 44 0 1793 421777 France 81 0 120 47 88 32 Japan fax only 1 6 TRAINING CLASSES In the U S and Canada...

Page 27: ......

Page 28: ...2 Overview of the 80C186 Family Architecture...

Page 29: ......

Page 30: ...ion Unit requires another opcode byte it takes the byte out of the prefetch queue The two units can operate independently of one another and are able under most circumstances to overlap instruction fe...

Page 31: ...Unit maintains the CPU status and control flags and manipulates the general reg isters and instruction operands All registers and data paths in the Execution Unit are 16 bits wide for fast internal t...

Page 32: ...2 Bus Interface Unit The 80C186 Modular Core and 80C188 Modular Core Bus Interface Units are functionally iden tical They are implemented differently to match the structure and performance characteris...

Page 33: ...C186 Modular Core family CPU has eight 16 bit general registers see Figure 2 3 The general registers are subdivided into two sets of four registers These sets are the data registers also called the H...

Page 34: ...egment registers contain the base addresses starting locations of these memory segments see Figure 2 4 The CS register points to the current code segment which contains instructions to be fetched The...

Page 35: ...Pointer but it can change be saved or be restored as a result of program execution For example if the Instruction Pointer is saved on the stack it is first automatically adjusted to point to the next...

Page 36: ...terrupt in this situation If the Sign Flag SF is set the high order bit of the result is a 1 Since negative binary numbers are represented in standard two s complement notation SF indicates the sign o...

Page 37: ...egment is composed of contiguous memory locations Segments are independent and sep arately addressable Software assigns every segment a base address starting location in memory space All segments begi...

Page 38: ...0 If TF is set the processor enters single step mode SF Sign Flag 0 If SF is set the high order bit of the result of an operation is 1 indicating it is negative ZF Zero Flag 0 If ZF is set the result...

Page 39: ...tween the CPU and memory use physical addresses Programs deal with logical rather than physical addresses Program code can be developed with out prior knowledge of where the code will be located in me...

Page 40: ...of a memory location can come from different sources depending on the type of reference that is being made see Table 2 2 Segment registers always hold the segment base addresses The Bus Interface Uni...

Page 41: ...2 12 Figure 2 8 Logical and Physical Address Physical Address Segment Base Logical Addresses 2C4H 2C3H 2C2H 2C1H 2C0H 2BFH 2BEH 2BDH 2BCH 2BBH 2BAH 2B9H 2B8H 2B7H 2B6H 2B5H 2B4H 2B3H 2B2H 2B1H 2B0H S...

Page 42: ...ically adjust the SI and DI registers as they process the strings one byte or word at a time When an instruction designates the Base Pointer BP register as a base register the variable is assumed to r...

Page 43: ...ide the current code segment All program offsets must be relative to the segment registers This allows the program to be moved anywhere in memory pro vided that the segment registers are updated to po...

Page 44: ...ck see Figure 2 10 by first decrementing the SP register by 2 and then writing the data word An element is popped off the stack by copying it from the top of the stack and then incrementing the SP reg...

Page 45: ...ck Bottom of stack POP AX POP BX TOS SS SP BB AA 10 50 1060 1062 105E 105B 105A 1058 1056 1054 1052 1050 22 00 44 66 88 AA 34 45 89 CD 33 11 55 77 99 BB 12 67 AB EF 12 34 1060 1062 105E 105B 105A 1058...

Page 46: ...ved into and out of reg isters This saves instructions registers and execution time in assembly language programs In high level languages where most variables are memory based compilers can produce fa...

Page 47: ...ing segment registers are also included in this group Figure 2 11 shows the flag storage formats The address object instructions manipulate the addresses of variables in stead of the values of the var...

Page 48: ...ed binary Signed binary integers Unsigned packed decimal Unsigned unpacked decimal A1014 0A U Undefined Value is indeterminate O Overflow Flag D Direction Flag I Interrupt Enable Flag T Trap Flag S Si...

Page 49: ...s and adjusts status flags accordingly Table 2 4 Arithmetic Instructions Addition ADD Add byte or word ADC Add byte or word with carry INC Increment byte or word by 1 AAA ASCII adjust for addition DAA...

Page 50: ...value or as a variable in the CL register This allows the shift count to be a supplied at execution time Arithmetic shifts can be used to multiply and divide bi nary numbers by powers of two Logical s...

Page 51: ...are loop The repetitions can be termi nated by a variety of conditions Repeated operations can be interrupted and resumed String instructions operate similarly in many respects see Table 2 8 A string...

Page 52: ...nstruction Pointer register points to the memory location of the next instruction to be fetched In most operating conditions the next instruction will already have been fetched and will be waiting in...

Page 53: ...is can be a problem when the CALL and RET instructions are in separately assembled programs The JMP instruction does not push any information onto the stack A JMP instruction can be NEAR or FAR Condit...

Page 54: ...E Jump if less not greater nor equal JLE JNG Jump if less or equal not greater JNC Jump if not carry JNE JNZ Jump if not equal not zero JNO Jump if not overflow JNP JPO Jump if not parity parity odd J...

Page 55: ...s in software or with an NMI Non Maskable Interrupt Table 2 10 Interpretation of Conditional Transfers Mnemonic Condition Tested Jump if JA JNBE CF or ZF 0 above not below nor equal JAE JNB CF 0 above...

Page 56: ...f the instruction set The following para graphs briefly describe register and immediate modes of operand addressing A detailed descrip tion of the memory and I O addressing modes is also provided 2 2...

Page 57: ...ter producing a 20 bit physical address One or more bus cycles are then run to access the operand The offset that the Execution Unit calculates for memory operand is called the operand s Effec tive Ad...

Page 58: ...he position of the operand s name a variable or label in the program The programmer can modify this value or explicitly specify the displacement A1015 0A CS 0000 0000 0000 0000 SS DS ES Assumed Unless...

Page 59: ...the displacement of the instruction Pro grammers typically use direct addressing to access scalar variables With register indirect addressing the effective address of a memory operand can be taken di...

Page 60: ...ures that may be located in different places in memory see Figure 2 16 A base register can be pointed at the structure Elements of the structure can then be addressed by their displacements Different...

Page 61: ...in an array see Figure 2 18 The displacement locates the beginning of the array and the value of the index register selects one element If the index register contains 0000H the processor selects the...

Page 62: ...gure 2 18 Accessing an Array with Indexed Addressing EA DI SI Opcode Mod R M Displacement or A1020 0A Displacement EA High Address Index Register 14 Array 8 Array 7 Array 6 Array 5 Array 4 Array 3 Arr...

Page 63: ...r can be used to access individual array elements Arrays contained in structures and matrices two dimensional arrays can also be accessed with based indexed addressing String instructions do not use n...

Page 64: ...with Based Index Addressing Displacement EA High Address Index Register 6 12 Base Register Displacement EA Index Register 6 Base Register Array 6 Array 5 Array 4 Array 3 Array 2 Array 1 Array 0 Parm 2...

Page 65: ...ber is an 8 bit immediate operand This allows fixed ac cess to ports numbered 0 to 255 Indirect I O port addressing is similar to register indirect address ing of memory operands The DX register conta...

Page 66: ...inal An unsigned 8 or 16 bit binary numeric value unsigned byte or word BCD A byte unpacked representation of a single decimal digit 0 9 ASCII A byte representation of alphanumeric and control charact...

Page 67: ...31 1 0 0 15 16 2 3 31 32 4 5 6 7 47 48 63 7 0 n 7 0 n 0 79 9 8 7 6 5 4 3 2 1 0 Most Significant Digit Least Significant Digit Byte Word n Byte Word 1 Byte Word 0 1 Signed Byte Signed Quad Word Unsigne...

Page 68: ...ne maskable interrupt request see Figure 2 24 This discussion covers only those areas of interrupts and exceptions that are common to the 80C186 Modular Core family The Interrupt Control Unit is proli...

Page 69: ...es 3FE 3FC 82 80 7E 7C 52 50 4E 4C 4A 48 46 44 42 40 3E 3C 3A 38 36 34 32 30 CS IP CS IP CS IP CS IP CS IP CS IP CS IP CS IP CS IP CS IP CS IP CS IP Type 11 DMA1 2E 2C 2A 28 26 24 22 20 1E 1C 1A 18 16...

Page 70: ...rrupt service routine The programmer must save usually by pushing onto the stack all registers used in the interrupt service routine otherwise their contents will be lost To allow nesting of maskable...

Page 71: ...Latency on page 2 45 The CPU au tomatically generates a type 2 interrupt vector The NMI input is asynchronous Setup and hold times are given only to guarantee recognition on a specific clock edge To b...

Page 72: ...n that caused the exception can be restarted Faults are detected and ser viced before the faulting instruction can be executed The return address pushed onto the stack in the interrupt processing inst...

Page 73: ...Relocation Register see Chapter 4 Peripheral Control Block When a floating point instruction is executed with the Escape Trap bit set the Escape Opcode fault occurs and the Escape Opcode service routi...

Page 74: ...C186 Modular Core family mem ber and a zero wait state external bus The execution time for an 80C188 Modular Core family member may be longer depending on the queue This is one factor in determining i...

Page 75: ...response time for the interrupts that supply their type Note that an on chip bus master such as the DRAM Refresh Unit can make use of idle bus cycles This can increase interrupt response time Figure...

Page 76: ...the maskable interrupt However a pending NMI can interrupt the CPU at any valid instruction boundary Therefore NMI can interrupt an excep tion service routine If an exception and NMI occur simultaneou...

Page 77: ...The maskable interrupt is serviced from within the single step service routine and that interrupt ser vice routine is not single stepped To prevent single stepping before an NMI the single step ser v...

Page 78: ...Push PSW CS IP Fetch Single Step Vector IRET Execute Single Step Service Routine Execute Single Step Service Routine Push PSW CS IP Fetch NMI Vector Interrupt Enable Bit IE 1 Trap Flag TF 1 Interrupt...

Page 79: ......

Page 80: ...3 Bus Interface Unit...

Page 81: ......

Page 82: ...provided within the memory and I O devices can directly connect to the address data bus or local bus The local bus can be demultiplexed with a single set of address latches to provide non multiplexed...

Page 83: ...o access even addressed 16 bit words two consecutive bytes with the least significant byte at an even address information is transferred over both halves of the data bus see Figure 3 3 A19 1 select th...

Page 84: ...3 3 BUS INTERFACE UNIT Figure 3 2 16 Bit Data Bus Byte Transfers Even Byte Transfer Odd Byte Transfer A19 1 D15 8 D7 0 A0 Low BHE High A19 1 D15 8 D7 0 A0 High BHE Low Y X Y 1 X 1 Y X Y 1 X 1 A1104 0A...

Page 85: ...devices e g ROM EPROM Flash During the byte read an external device can drive both halves of the bus and the BIU automatically accesses the correct half During the byte write op eration the BIU drives...

Page 86: ...te and word transfers to even or odd addresses all transfer data over the same 8 bit bus Byte transfers to even or odd addresses transfer information in one bus cycle Word transfers to even or odd add...

Page 87: ...memory cycles Memory mapped I O allows the full power of the instruction set to be used when communicating with peripheral devices I O read and I O write bus cycles use a separate I O address space On...

Page 88: ...ressed word data 3 3 2 8 Bit Bus Memory and I O Requirements An 8 bit bus interface has no restrictions on implementing the memory or I O interfaces All transfers bytes and words occur over the single...

Page 89: ...T3 and T4 A TI idle state occurs when no bus cycle is pending Multiple T3 states occur to generate wait states The TW symbol represents a wait state The operation of a bus cycle can be separated into...

Page 90: ...2 and continues through T4 Figure 3 9 illustrates the T state relationship of the two phases Figure 3 8 BIU State Diagram Bus Ready Request Pending HOLD Deasserted Bus Not Ready Halt Bus Cycle Bus Rea...

Page 91: ...E provides a strobe to latch physical address information Address is presented on the multi plexed address data bus during T1 see Figure 3 10 The falling edge of ALE occurs during the middle of T1 and...

Page 92: ...Valid Valid NOTES 1 TCHLH TCHSV Clock high to ALE high S2 0 valid 2 TCLAV Clock low to address valid BHE valid 3 TAVLL Address valid to ALE low address setup to ALE 4 TCHLL Clock high to ALE low 5 TCL...

Page 93: ...2 S1 S0 0 0 0 Interrupt Acknowledge 0 0 1 I O Read 0 1 0 I O Write 0 1 1 Halt 1 0 0 Instruction Prefetch 1 0 1 Memory Read 1 1 0 Memory Write 1 1 1 Idle passive 4 I I STB 8 8 O O ALE Latched Address S...

Page 94: ...before T4 or TI 3 4 3 Wait States Wait states extend the data phase of the bus cycle Memory and I O devices that cannot provide or accept data in the minimum four CPU clocks require wait states Figur...

Page 95: ...Valid Read Data Valid Write Data NOTES 1 TCLRL CLWL TCLOV Clock low to valid RD WR active write data valid 2 TCLSH Clock low to status inactive 3 TDVCL Data input valid to clock low 4 TCLRH CLWH Clock...

Page 96: ...Bus Cycle with Wait States Figure 3 14 ARDY and SRDY Pin Block Diagram ALE S2 0 A19 16 AD15 0 READY WR CLKOUT T1 T2 T3 TW TW T4 Valid Address Address Valid Write Data A1040 0A D Q ARDY BUS READY CLKOU...

Page 97: ...s in no wait states Figure 3 15 Generating a Normally Not Ready Bus Signal A normally ready signal remains high at all times except when the selected device needs to signal a not ready condition For a...

Page 98: ...is inactive prior to the phase 2 clock edge or ARDY is inactive prior to the phase 1 clock edge A single latch captures the state of the SRDY input see Figure 3 14 on page 3 15 SRDY must be valid by t...

Page 99: ...ance suffers because the instruction prefetch queue cannot be kept full Integrated peripheral perfor mance suffers because the maximum bus bandwidth decreases 3 4 4 Idle States Under most operating co...

Page 100: ...CLKOUT In a Normally Ready system a wait state will be inserted when 1 2 are met Assumes SRDY is low T2 T3 TW ARDY CLKOUT Alternatively in a Normally Ready system a wait state will be inserted when1 2...

Page 101: ...ates a typical read cycle Table 3 2 lists the three types of read bus cycles Figure 3 20 illustrates a typical 16 bit interface connection to a read only device interface The same example applies to a...

Page 102: ...han the equation result indicates a buffer fight A buffer fight means two or more devices are driving the bus at the same time This can lead to short circuit conditions resulting in large current spik...

Page 103: ...alue on the bus is ignored RFSH has the same bus timing as BHE Figure 3 20 Read Only Device Interface 3 5 2 Write Bus Cycles Figure 3 21 illustrates a typical write bus cycle The bus cycle starts with...

Page 104: ...Cycle Types Status Bits Bus Cycle Type S2 S1 S0 0 1 0 Write I O Initiated by executing IN OUT INS OUTS instructions or by the DMA Unit A15 0 select the desired I O port A19 16 are driven to zero see...

Page 105: ...rising edge of WR TAW TCW and TDW de fine the minimum data setup requirements The value calculated by their respective equations must be greater than the device requirements To increase the calculate...

Page 106: ...l Unit for more information The BIU controls the bus cycles required to fetch vector infor mation from the peripheral device then passes the information to the CPU These bus cycles collectively known...

Page 107: ...Bus Cycle T1 T2 T3 T4 CLKOUT ALE TI TI T1 T2 T3 AD15 0 AD7 0 RD WR BHE DEN DT R LOCK S2 0 INTA0 INTA1 A19 16 A15 8 NOTE Vector Type is read from AD7 0 only INTA occurs during T2 in slave mode Note A15...

Page 108: ...bus cycles However you can add wait states to interrupt acknowledge cycles if the PCB is located at any other address 3 5 3 1 System Design Considerations Although ALE is generated for both bus cycle...

Page 109: ...next bus cycle to be executed by the BIU Under most instruction sequences the BIU floats the address data bus because the next operation would most likely be an instruction prefetch However if the HAL...

Page 110: ...5 0 AD7 0 A15 8 A19 16 NOTES 1 The AD15 0 AD7 0 bus can be floating driving a previous write data value or driving the next instruction prefetch address value For an 8 bit device A15 8 drives either t...

Page 111: ...agement mode The BIU returns to the HALT bus state after it completes the desired bus operation However the BIU does not execute another bus HALT cycle i e ALE and bus cycle status are not regenerated...

Page 112: ...e CLKOUT AD15 0 AD7 0 ALE A15 8 A19 16 Address Note 1 Note 2 Note 3 NOTES 1 Previous bus cycle value 2 Only occurs for BHE on the first refresh bus cycle after entering HALT 3 BHE 1 for 16 bit device...

Page 113: ...occur after exiting HALT are read cycles to reload the CS IP registers Figure 3 29 shows how the HALT bus state is exited when an NMI or INTn occurs T1 T2 T3 T4 T1 T2 T3 TI CLKOUT AD15 0 AD7 0 TI TI A...

Page 114: ...device performance and off board de vice interfaces may not be supported directly without modifying the BIU interface The following sections deal with topics to enhance or modify the operation of the...

Page 115: ...or I O device cannot float its outputs in time to prevent bus contention even at reset Figure 3 30 DEN and DT R Timing Relationships The circuit shown in Figure 3 31 illustrates how to use transceive...

Page 116: ...bus accesses Figure 3 32 illustrates how to use chip selects to qualify DEN DT R always connects directly to the transceiver However an inverter may be required if the po larity of DT R does not matc...

Page 117: ...s occurs then continue program execution One way to synchronize software execution with hardware events requires the use of interrupts Executing a HALT instruction suspends program execution until an...

Page 118: ...ystem operation priority of the shared system bus is determined by the arbitration circuits on a cycle by cycle basis As each CPU requires a transfer over the sys tem bus it requests access to the bus...

Page 119: ...not require these signals because they use the 80187 math coprocessor which has an I O port interface similar to that of a peripheral device The queue status signals QS0 and QS1 indicate the state of...

Page 120: ...ing the bus After HLDA goes active the requesting device can take control of the local bus and remains in control of the bus until HOLD is removed 3 7 1 Entering Bus HOLD In responding to the hold req...

Page 121: ...ld request occurs just before the BIU begins another bus cycle Table 3 8 Signal Condition Entering HOLD Signal HOLD Condition A19 16 S2 0 RD WR DT R BHE RFSH LOCK These signals float one half clock be...

Page 122: ...DMA request or refresh bus cycle has completed Refresh bus cycles have a higher priority than hold bus requests A bus hold request cannot separate the bus cycles associated with a DMA transfer worst c...

Page 123: ...short HLDA pulse and continues to wait for HLDA to be asserted while the BIU waits for HOLD to be deasserted The circuit shown in Figure 3 36 can be used to latch HLDA HLDA CLKOUT HOLD NOTES 1 HLDA is...

Page 124: ...D go active before the refresh bus cycle is complete the BIU will release the bus and generate HLDA 3 7 2 Exiting HOLD Figure 3 37 shows the timing associated with exiting the bus hold state Normally...

Page 125: ...hest to lowest 1 Instruction execution read write following a non pipelined effective address calculation 2 Refresh bus cycles 3 Bus hold request 4 Single step interrupt vectoring sequence 5 Non Maska...

Page 126: ...code execution The following points apply to sequences of related execution cycles The second read write cycle of an odd addressed word operation is inseparable from the first bus cycle The second rea...

Page 127: ......

Page 128: ...4 Peripheral Control Block...

Page 129: ......

Page 130: ...ters that cover the associated peripheral Accessing the Peripheral Con trol Block on page 4 4 discusses how the registers are accessed and outlines considerations for reading and writing them 4 2 PCB...

Page 131: ...ve mode If SL is clear it operates in master mode MEM Memory I O 0 If MEM is set the PCB is located in memory space If MEM is clear the PCB is located in I O space R19 8 PCB Base Address Upper Bits 0F...

Page 132: ...Reserved 58H T1CNT 98H Reserved D8H D1TC 1AH Reserved 5AH T1CMPA 9AH Reserved DAH D1CON 1CH Reserved 5CH T1CMPB 9CH Reserved DCH Reserved 1EH Reserved 5EH T1CON 9EH Reserved DEH Reserved 20H Reserved...

Page 133: ...Peripheral Control Block Address data and control information is driven on the external pins as with an ordinary bus cycle Information returned by an external device is ignored even if the access doe...

Page 134: ...addresses work normally but only a byte will be read For example IN AL DX will not transfer DX into AX only AL is modified No problems will arise if the following recommendations are adhered to Word...

Page 135: ...ns should be used for the registers in the Peripheral Control Block of an 80C188 Modular Core family member This requires half the bus cycles of word operations Byte opera tions are valid only for eve...

Page 136: ...5 1 Considerations for the 80C187 Math Coprocessor Interface Systems using the 80C187 math coprocessor interface must not relocate the Peripheral Control Block to location 0000H in I O space The 80C1...

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Page 138: ...5 ClockGenerationand Power Management...

Page 139: ......

Page 140: ...he clock generation circuit Figure 5 1 includes a crystal oscillator a divide by two counter and power save and reset circuitry See Power Save Mode on page 5 11 for a discussion of Power Save mode as...

Page 141: ...l is reactive and forces the oscillator back toward the crystal s nominal frequency Figure 5 2 Ideal Operation of Pierce Oscillator Figure 5 3 shows the actual microprocessor crystal connections For l...

Page 142: ...kes the circuit capacitive at the third overtone frequency necessary for oscil lation The two capacitors and inductor at X2 plus some stray capacitance approximately equal the 20 pF load capacitor CX2...

Page 143: ...Ceq at the operation frequency The desired operation frequency is the third overtone frequency marked on the crystal Optimiz ing equations for the above three criteria yields Table 5 1 This table sho...

Page 144: ...R is proportional to crystal thickness inversely proportional to frequency A lower value gives a faster startup time but the specification is usually not important in microprocessor applications Shunt...

Page 145: ...practically any duty cycle provid ed it meets the minimum high and low times stated in the data sheet Selecting an external clock oscillator is more straightforward than selecting a crystal 5 1 3 Outp...

Page 146: ...s The device pins will assume their reset states on the second falling edge of X1 following the assertion of RES Figure 5 5 Simple RC Circuit for Powerup Reset The processor exits reset identically in...

Page 147: ...cc and X1 stable to RES high approximately 32 X1 periods UCS LCS MCS3 0 NCS TMR OUT0 TMR OUT1 PCS6 0 NOTE CLKOUT synchronization occurs 1 1 2 X1 periods after RES is sampled low X1 CLKOUT A19 16 RESET...

Page 148: ...periods after recognition of RES in the logic high state If an alternate bus master asserts HOLD during reset the processor immediately asserts HLDA and will not prefetch instructions A1522 0B RES AD1...

Page 149: ...gh delay the processor is likely to lose its present state needing a reset to resume normal operation An 80C186 Modular Core microprocessor is fully static The CPU stores its current state in flip flo...

Page 150: ...nal oscillator frequency were lower by the same amount Since the processor is static a lower limit clock frequency does not apply It may be necessary to repro gram integrated peripherals such as the T...

Page 151: ...efined by F1 0 Clearing this bit disables Power Save mode and forces the CPU to operate at full speed PSEN is automatically cleared whenever an interrupt occurs F1 0 Clock Division Factor 0H These bit...

Page 152: ...rrupts If an NMI occurs or an unmasked interrupt request has sufficient priority to pass to the core Power Save mode will end The PSEN bit clears and the clock resumes full speed operation at the fall...

Page 153: ...qu 8000H Power Save enable bit data segment public data FreqTable dw 1 4 8 16 32 64 0 0 data ends lib_80C186 segment public code assume cs lib_80C186 ds data public _power_save _power_save proc far pu...

Page 154: ...6 Chip Select Unit...

Page 155: ......

Page 156: ...bles the SRAM device Also note that any bus cycle with an address starting at 30000H 50000H 70000H and so on also selects the SRAM device Decoding more address bits solves the problem of a chip select...

Page 157: ...coder circuits The Chip Select Unit activates a chip select for bus cycles initiated by the CPU DMA Control Unit or Refresh Control Unit Six of the chip selects map only into memory address space whil...

Page 158: ...S MCS3 MCS2 MCS1 MCS0 Base Base 0 Base 128 Base 256 Base 384 Base 512 Base 640 Base 768 PCS0 PCS1 PCS2 PCS3 PCS4 Base PCS5 PCS6 MUX A B A B A1 A2 EX Control Bit Internal Address Bit Memory I O Selecto...

Page 159: ...starting address is programmed in the UMCS register Figure 6 5 on page 6 7 The LCS chip select al ways starts at address location 0H its block size and thus its ending address is programmed in the LM...

Page 160: ...enabled 2 The bus cycle status matches the default or programmed type memory or I O 3 The bus cycle address is within the default or programmed block size 4 The bus cycle is not accessing the Peripher...

Page 161: ...6 4 1 Initialization Sequence Chip selects do not have to be initialized in any specific order However the following guidelines help prevent a system failure 1 Initialize local memory chip selects 2...

Page 162: ...sable 0H When R2 is clear bus ready must be active to complete a bus cycle When R2 is set R1 0 control the number of bus wait states and bus ready is ignored R1 0 Wait State Value 3H R1 0 define the m...

Page 163: ...When R2 is clear bus ready must be active to complete a bus cycle When R2 is set R1 0 control the number of bus wait states and bus ready is ignored R1 0 Wait State Value 3H R1 0 define the minimum nu...

Page 164: ...able X When R2 is clear bus ready must be active to complete a bus cycle When R2 is set R1 0 control the number of bus wait states and bus ready is ignored R1 0 Wait State Value 3H R1 0 define the min...

Page 165: ...R2 Bus Ready Disable X When R2 is clear bus ready must be active to complete a bus cycle When R2 is set R1 0 control the number of bus wait states and bus ready is ignored R1 0 Wait State Value 3H R1...

Page 166: ...CS6 4 X Applies only to PCS6 4 When R2 is clear bus ready must be active to complete a bus cycle When R2 is set R1 0 control the number of bus wait states and bus ready is ignored R1 0 Wait State Valu...

Page 167: ...ng or ending addresses and block sizes This section describes how to control the active range of each chip select 6 4 2 1 UCS Active Range The UCS starting address is 100000H 1 Mbyte minus the block s...

Page 168: ...and the block size programmed in the MPCS register see Table 6 4 and Figure 6 10 The base address must be an integer multiple of the block size Table 6 5 lists the allowable block sizes and base addr...

Page 169: ...o 0 0 1 X X X X 128 U16 13 must be zero 0 1 X X X X X 256 U17 13 must be zero 1 X X X X X X 512 U18 13 must be zero NOTE If U19 is one will overlap UCS X don t care but should be 0 for future compatib...

Page 170: ...eripheral devices operate properly using three or fewer wait states However accessing such devices as a dual port memory an expansion bus interface a system bus interface or remote peripheral devices...

Page 171: ...led chip selects programmed to cover the same physical address space This is true if any portion of the chip selects address ranges overlap i e chip selects ranges do not need to overlap completely to...

Page 172: ...bus cycles The PCS chip selects activate for either memory or I O bus cycles depending on the state of the MS bit in the MPCS register Figure 6 9 on page 6 11 Memory bus cycles consist of memory read...

Page 173: ...hip Selects During HOLD 6 6 EXAMPLES The following sections provide examples of programming the Chip Select Unit to meet the needs of a particular application The examples do not go into hardware anal...

Page 174: ...UNIT Figure 6 13 Typical System L a t c h Processor ALE AD Bus Addr Bus PCS1 DRQ CE D R A M 256K ARDY 20 MCS3 0 UCS PCS0 LCS SRAM 32K Floppy Disk Control CE CE EPROM 128K CE DRQ DACK A0 A19 16 AD15 0...

Page 175: ...1024 EPROM_SIZE Start address in Kbytes EPROM_WAIT EQU 1 Wait states The UMCS register values are calculated using the above system contraints and the equations below UMCS_VAL EQU EPROM_BASE SHL 6 OR...

Page 176: ...E OR PCS_FUNC OR IO_RDY OR IO_WAIT I O is selected using the PCS0 chip select Wait states assume operation at 16 MHz For this example the Floppy Disk Controller is connected to PCS2 and PCS1 provides...

Page 177: ...elect mov ax PACS_VAL out dx al CODE ENDS Power on reset code to get started ASSUME CS POWER_ON POWER_ON SEGMENT AT 0FFFFH mov dx UMCS_REG point to UMCS register mov ax UMCS_VAL reprogram UMCS to matc...

Page 178: ...7 Refresh Control Unit...

Page 179: ......

Page 180: ...tegrating the Refresh Control Unit into the processor allows an external DRAM controller to use chip selects wait state logic and status lines Figure 7 1 Refresh Control Unit Block Diagram Refresh Clo...

Page 181: ...9 bit address counter forms the refresh addresses supporting any dynamic memory devices with up to 9 rows of memory cells 9 refresh address bits This includes all practical DRAM sizes for the process...

Page 182: ...er wise the time between refresh requests would be a function of varying bus activity When the BIU services the refresh request it clears the request and increments the refresh address Counter Load Co...

Page 183: ...on page 7 8 Figure 7 3 Refresh Address Formation Refresh address bits RA12 10 are always zero A linear feedback shift counter generates address bits RA9 1 and RA0 is always one The counter does not c...

Page 184: ...ular Core family DRAM interfaces use only this method Others are not dis cussed here The DRAM controller s purpose is to use the processor s address status and control lines to gen erate the multiplex...

Page 185: ...e CAS When CAS is present the dummy read cycle becomes a true read cycle the DRAM drives the bus and the DRAM row still gets refreshed Both RAS and CAS stay active during any wait states They go inact...

Page 186: ...mine the correct value for the RFTIME Register value Figure 7 5 Formula for Calculating Refresh Interval for RFTIME Register If the processor enters Power Save mode the refresh rate must increase to o...

Page 187: ...defines the time between refresh requests The higher the value the longer the time between requests The down counter decrements every fall ing CLKOUT edge regardless of core activity When the counter...

Page 188: ...esh Control Unit clears both the counter and the corresponding counter bits in the control register Register Name Refresh Clock Interval Register Register Mnemonic RFTIME Register Function Sets refres...

Page 189: ...ontrols Refresh Unit operation Bit Mnemonic Bit Name Reset State Function REN Refresh Control Unit Enable 0 Setting REN enables the Refresh Unit Clearing REN disables the Refresh Unit RC8 0 Refresh Co...

Page 190: ...M to refresh clock_time DRAM refresh rate OUTPUTS None NOTE Parameters are passed on the stack as required by high level languages RFBASE equ xxxxh substitute register offset RFTIME equ xxxxh RFCON eq...

Page 191: ...ernate master removes HOLD The user must design the system so that the processor can re gain bus control If the alternate master asserts HOLD after the processor starts the refresh cycle the CPU will...

Page 192: ...rted signaling need to run DRAM refresh cycles less than TCLHAV 2 External bus master terminates use of the bus 3 HOLD deasserted greater than THVCL 4 Hold may be reasserted after one clock 5 Lines co...

Page 193: ......

Page 194: ...8 Interrupt Control Unit...

Page 195: ......

Page 196: ...8259A See Figure 8 15 on page 8 24 This mode can be useful in larger system designs The Interrupt Control Unit has the following features Programmable priority of each interrupt source Individual mask...

Page 197: ...diagram of the Interrupt Control Unit in Master mode In this mode the ICU processes all interrupt requests both external and internal The three timer interrupt requests share a single input while the...

Page 198: ...able or unmask enable each interrupt source by setting or clearing the corresponding bit in the Interrupt Mask register 8 2 1 2 Interrupt Priority One critical function of the Interrupt Control Unit i...

Page 199: ...rogrammer explicitly enables interrupts Enabling maskable in terrupts within an interrupt handler allows interrupts to be nested Otherwise interrupts are pro cessed sequentially one interrupt handler...

Page 200: ...e interrupt acknowledge the Interrupt Control Unit clears the corresponding bit in the Interrupt Request register and sets the corresponding bit in the In Service register The In Service register keep...

Page 201: ...the interrupt type in this case type 12 to the CPU 5 The Interrupt Control Unit clears the INT0 bit in the Interrupt Request register and sets the INT0 bit in the In Service register 6 The CPU execut...

Page 202: ...the Interrupt Request bit remains set When the timer interrupt is acknowledged the shared In Service bit is set No other timer inter rupts can occur when the In Service bit is set If a second timer i...

Page 203: ...interrupt from the 8259A While the interrupt handler is executing the 8259A receives a higher priority interrupt from one of its sourc es The 8259A applies its own priority criteria to that interrupt...

Page 204: ...s case the CPU runs an external interrupt acknowledge cycle to fetch the interrupt type from the 8259A see Interrupt Acknowledge Bus Cycle on page 3 25 8 3 5 Polling In some applications it is desirab...

Page 205: ...riggered interrupt is generated by a valid logic one on the external interrupt pin The pin must remain high until after the CPU acknowledges the interrupt Unlike edge triggered inter rupts level trigg...

Page 206: ...8 3 Interrupt Control Unit Registers in Master Mode Register Name Offset Address INT3 Control 3EH INT2 Control 3CH INT1 Control 3AH INT0 Control 38H DMA0 Control 34H DMA1 Control 36H Timer Control 32H...

Page 207: ...mask bit is the same as the one in the Interrupt Mask register Modifying a bit in either register also mod ifies that same bit in the other register The Interrupt Control registers for the external in...

Page 208: ...register for the internal interrupt sources Bit Mnemonic Bit Name Reset State Function MSK Interrupt Mask 1 Clear to enable interrupts from this source PM2 0 Priority Level 111 Defines the priority l...

Page 209: ...pins Bit Mnemonic Bit Name Reset State Function LVL Level trigger 0 Selects the interrupt triggering mode 0 edge triggering 1 level triggering MSK Interrupt Mask 1 Clear to enable interrupts from thi...

Page 210: ...CAS Cascade Mode 0 Set to enable cascade mode LVL Level trigger 0 Selects the interrupt triggering mode 0 edge triggering 1 level triggering The LVL bit must be set when external 8259As are cascaded...

Page 211: ...Set a mask bit to disable interrupts from the corresponding source The mask bit is the same as the one in the Interrupt Control register Modifying a bit in either register also modifies that same bit...

Page 212: ...ables all interrupts of any priority Register Name Interrupt Mask Register Register Mnemonic IMASK Register Function Masks individual interrupt sources Bit Mnemonic Bit Name Reset State Function INT3...

Page 213: ...The Interrupt Control Unit uses the In Service register to support interrupt nesting Register Name Priority Mask Register Register Mnemonic PRIMSK Register Function Masks lower priority interrupt sou...

Page 214: ...Function Indicates which interrupt handlers are in process Bit Mnemonic Bit Name Reset State Function INT3 0 External Interrupt In Service 0000 0 A bit is set to indicate that the corresponding extern...

Page 215: ...upt Reading the Poll Status register Figure 8 12 will merely transmit the status of the polling bits without modifying any of the other Interrupt Controller registers Figure 8 11 Poll Register Registe...

Page 216: ...0 bits with the interrupt type of the interrupt whose In Service bit you wish to clear For example to clear the In Service bit for INT2 write 000EH to the EOI reg ister The timer interrupts share an...

Page 217: ...t and is cleared when the interrupt request is acknowledged Any number of bits can be set at any one time Register Name End of Interrupt Register Register Mnemonic EOI Register Function Used to issue...

Page 218: ...t processes only the internal interrupt re quests and acts as an interrupt input to the external 8259A In simplest terms the Interrupt Control Unit behaves like a cascaded 8259A to the master 8259A Se...

Page 219: ...INTERRUPT CONTROL UNIT 8 24 Figure 8 15 Interrupt Control Unit in Slave Mode 8259A 82C59A INT INTA Cascade Address Decode INT0 INTA Select 80186 Modular Core VCC IRQ A1194 A0...

Page 220: ...NT0 Control registers with individual Timer 0 Timer 1 and Timer 2 Control registers The remaining registers retain the same functions as in Master mode however some bit positions change to accommodate...

Page 221: ...B Offset Address INT3 Control not used 3EH INT2 Control not used 3CH INT1 Control Timer 2 Control 3AH INT0 Control Timer 1 Control 38H DMA1 Control DMA1 Control 36H DMA0 Control DMA0 Control 34H Timer...

Page 222: ...5 to the VT2 0 bits Register Name Interrupt Vector Register Slave Mode only Register Mnemonic INTVEC Register Function Specifies the five most significant bit of the interrupt vector types for the in...

Page 223: ...s the bit positions for Slave mode Figure 8 19 Request Mask and In Service Registers Register Name End of Interrupt Register in Slave Mode Register Mnemonic EOI Register Function Used to issue the EOI...

Page 224: ...e slave select input to the Interrupt Control Unit During the second inter rupt acknowledge cycle the highest priority slave interrupt controller transfers the interrupt type of its highest priority i...

Page 225: ...nterrupt Control register for each interrupt source For external interrupt pins select edge or level triggering For INT0 or INT1 enable cascade mode special fully nested mode or both if you wish to us...

Page 226: ...errupt controller to provide two cascaded interrupt inputs through an external 8259A connected to INT0 and INTA0 and two direct interrupt inputs connected to INT1 and INT3 The default priorities are u...

Page 227: ......

Page 228: ...9 Timer Counter Unit...

Page 229: ......

Page 230: ...at the end see Figure 9 2 No connection exists between the counter element s se quencing through timer register banks and the Bus Interface Unit s sequencing through T states Timer operation and bus i...

Page 231: ...ter Unit Block Diagram Transition Latch Synchronizer Transition Latch Synchronizer Timer 0 Registers Timer 1 Registers Timer 2 Registers Output Latch Output Latch T0 Out T1 Out Counter Element CPU Int...

Page 232: ...T1IN resolution time setup time not met 3 Modified count value written into Timer 0 count register 4 T1IN resolution time count value written into Timer 1 count register 5 T1IN resolution time T0OUT T...

Page 233: ...o Hi transition on input pin since last service Done External Clocking EXT 1 Retrigger RTG 1 Yes No No Yes Yes Did Timer 2 Reach Maxcount Last Service State Prescaler On P 1 Lo to Hi transition on inp...

Page 234: ...Use A Counter Compare B Counter Compare A Continuous Mode CONT 1 Yes No Done Clear RIU Bit TOUT Pin Driven High Continued From A No Yes Done Clear Enable Bit Stop Counting No Continuous Mode CONT 1 Ye...

Page 235: ...nly in single maximum count mode Figure 9 4 It can be used as a free running clock and as a prescaler to Timers 0 and 1 Timer 2 can be clocked only internally at CLKOUT frequency Timer 2 can also gene...

Page 236: ...uest when the Count register equals a Maximum Count register Clear to disable interrupt requests RIU Register In Use X Indicates which compare register is in use When set the current compare register...

Page 237: ...KOUT This bit is ignored with external clocking EXT 1 EXT External Clock X Set to use external clock clear to use internal clock The RTG and P bits are ignored with external clocking EXT set ALT Alter...

Page 238: ...rupt request when the Count register equals a Maximum Count register Clear to disable interrupt requests MC Maximum Count X This bit is set when the counter reaches a maximum count The MC bit must be...

Page 239: ...NT T1CNT T2CNT Register Function Contains the current timer count Bit Mnemonic Bit Name Reset State Function TC15 0 Timer Count Value XXXXH Contains the current count of the associated timer 15 0 T C...

Page 240: ...nt Compare A and B 4 Program the Timer Control register to enable the timer When using Timer 2 to prescale another timer enable Timer 2 last If Timer 2 is enabled first it will be at an unknown point...

Page 241: ...cing scheme Timer 2 can use only the internal clock as a timer event Timers 0 and 1 can also use Timer 2 reaching its maximum count as a timer event In this config uration Timer 0 or Timer 1 increment...

Page 242: ...used The timer will count to the value contained in Maxcount Compare A and reset to zero Timer 2 can operate only in this mode Timers 0 and 1 can also use dual maximum count mode In this mode Maxcount...

Page 243: ...ccurs one clock after the counter element services the timer when the maximum count is reached see Figure 9 9 With external clocking the time between a transition on a timer input and the correspondin...

Page 244: ...timer has an Enable EN bit in its Control register to allow or prevent timer counting The Inhibit INH bit controls write accesses to the EN bit Timers 0 and 1 can be programmed to use their input pin...

Page 245: ...is generated each time the value in Maxcount Compare A or Max count Compare B is reached If the interrupt is disabled after a request has been generated but before a pending interrupt is serviced the...

Page 246: ...it Application Examples The following examples are possible applications of the Timer Counter Unit They include a real time clock a square wave generator and a digital one shot 9 3 3 Real Time Clock E...

Page 247: ...me to second second to set time to T2Compare T2CMPA value see note below OUTPUTS None NOTE Parameters are passed on the stack as required by high level languages For a CLKOUT of 16Mhz f timer2 16Mhz 4...

Page 248: ...r ax ax set interrupt vector mov ds ax mov si 4 timer_2_int mov word ptr ds si offset timer_2_interrupt_routine inc si inc si mov ds si cs pop ds mov ax hour set time mov _hour al mov ax minute mov _m...

Page 249: ...t_ctl bump_second mov _msec 0 reset millisecond cmp _minute 59 has 1 minute passed jae bump_minute inc _second jmp short reset_int_ctl bump_minute mov _second 0 reset second cmp _minute 59 has 1 hour...

Page 250: ...S None NOTE Parameters are passed on the stack as required by high level Languages T1CMPA equ xxxxH substitute register offsets T1CMPB equ xxxxH T1CNT equ xxxxH T1CON equ xxxxH lib_80186 segment publi...

Page 251: ...n SYNTAX extern void far one_shot int CMPB INPUTS CMPB This is the T1CMPB value required to generate a pulse of a given pulse width This value is calculated from the formula below CMPB req_pulse_width...

Page 252: ...dx al mov dx T1CMPA set time before t_shot to 0 mov ax 1 out dx al mov dx T1CMPB set pulse time mov ax _CMPB out dx al mov dx T1CON mov ax C002H start Timer 1 out dx al CountDown in ax dx read in T1C...

Page 253: ......

Page 254: ...10 Direct Memory Access Unit...

Page 255: ......

Page 256: ...en releases con trol of the bus and the DMA controller performs the transfer In many cases the CPU releases the bus and continues to execute instructions from the prefetch queue If the DMA transfers a...

Page 257: ...exceeded its programmed transfer limit Every DMA transfer consists of two distinct bus cycles a fetch and a deposit see Figure 10 1 on page 10 2 During the fetch cycle the byte or word is read from th...

Page 258: ...t pointer for the source of data and a twenty bit pointer for the destination of data The twenty bit pointers allow access to the full 1 Mbyte of memory space The DMA Unit views memory as a linear uns...

Page 259: ...t is sending data For example a disk controller in the process of reading data from a disk would use a source synchronized request data would be moving from the disk to memory A destination synchroniz...

Page 260: ...states at the end of the deposit cycle Figure 10 4 The two idle states extend the DMA cycle to allow the destination device to deassert its DRQ pin four clocks before the end of the cycle If the two...

Page 261: ...ld point to the waveform data the destination would point to the A D converter and Timer 2 would request a transfer every 22 microseconds See Timed DMA Transfers on page 10 26 10 1 5 2 Unsynchronized...

Page 262: ...disarms itself when the transfer count value reaches zero No further DMA transfers take place on the channel until it is re armed by direct programming Unsynchronized transfers always terminate when t...

Page 263: ...ognize DMA cycles that access I O space above 64K 10 1 10 The Two Channel DMA Unit Two DMA channels are combined with arbitration logic to form the DMA Unit see Figure 10 5 10 1 10 1 DMA Channel Arbit...

Page 264: ...ree to perform its transfer even though the higher priority channel has not completed all of its transfers Channel 1 regains the bus at the end of channel 0 s trans fer The transfers will alternate as...

Page 265: ...A total of six Peripheral Control Block registers configure each DMA channel 10 2 1 DMA Channel Parameters The first step in programming the DMA Unit is to set up the parameters for each channel 10 2...

Page 266: ...in the normal 64K I O space only the high order bits in the pointer registers must be cleared Figure 10 7 DMA Source Pointer High Order Bits Register Name DMA Source Address Pointer High Register Mnem...

Page 267: ...crement and decrement bits for a pointer are programmed to the same value then the pointer remains constant The programmed data width byte or word for the channel automatically controls the amount tha...

Page 268: ...bits of the DMA Destination pointer Bit Mnemonic Bit Name Reset State Function DDA19 16 DMA Destination Address XXXXH DDA19 16 are driven on A19 16 during the deposit phase of a DMA transfer NOTE Res...

Page 269: ...increment or decrement the pointer registers by two for each transfer while byte trans fers modify the pointer registers by one Register Name DMA Destination Address Pointer Low Register Mnemonic DxDS...

Page 270: ...e destination pointer after each transfer See Note SMEM Source Address Space Select X Selects memory or I O space for the source pointer Set SMEM to select memory space clear SMEM to select I O space...

Page 271: ...ynchronization SYN1 SYN0 Synchronization Type 0 0 Unsynchronized 0 1 Source synchronized 1 0 Destination synchronized 1 1 Reserved do not use P Relative Priority X Set P to select high priority for th...

Page 272: ...e DMA Control Register Register Mnemonic DxCON Register Function Controls DMA channel parameters Bit Mnemonic Bit Name Reset State Function CHG Change Start Bit X Set CHG to enable modifying the STRT...

Page 273: ...er Figure 10 11 on page 10 15 NOTE The combination SYN1 0 11 is reserved and will result in unpredictable operation When IDRQ is set internal requests selected the channel must always be programmed fo...

Page 274: ...DMA Control Register Figure 10 11 on page 10 15 must be set to generate an interrupt request 10 2 1 8 Setting the Relative Priority of a Channel The priority of a channel is controlled by the Priority...

Page 275: ...function when the interrupt controller is in slave mode 10 2 3 Initializing the DMA Unit Use the following sequence when programming the DMA Unit 1 Program the source and destination pointers for all...

Page 276: ...s The maximum DMA transfer rate is a function of processor operating frequency and synchroni zation mode For unsynchronized and source synchronized transfers the 80C186 Modular Core can transfer two b...

Page 277: ...A is in progress Latched status line S6 can be used as a qualifier to the chip select for situations in which the chip select line will be ac tive for both DMA and normal data accesses 10 4 DMA UNIT E...

Page 278: ...A_1 to DEST_DATA_1 The first step is to calculate the proper values for the source and destination pointers MOV AX SEG SOURCE_DATA_1 ROL AX 4 GET HIGH 4 BITS MOV BX AX SAVE ROTATED VALUE AND AX 0FFF0H...

Page 279: ...SYNCHRONIZED BURST IS NOW RUNNING ON THE BUS NOW SET UP CHANNEL 1 TO SERVICE THE DISK CONTROLLER FOR THIS EXAMPLE WE WILL ONLY BE READING FROM THE DISK THE SOURCE IS THE I O PORT FOR THE DISK CONTROLL...

Page 280: ...E MEMORY SPACE I O SPACE INCREMENT PTR CONSTANT PTR TERMINATE ON TC INTERRUPT SOURCE SYNC HIGH PRIORITY RELATIVE TO CHANNEL 0 BYTE XFERS USE DRQ PIN FOR REQUEST SOURCE ARM CHANNEL MOV AX 1010001101100...

Page 281: ...ROL AX 4 GET HIGH 4 BITS MOV BX AX SAVE ROTATED VALUE AND AX 0FFF0H GET SHIFTED LOW 4 NIBBLES ADD AX OFFSET WAVEFORM_DATA NOW LOW BYTES OF POINTER ARE IN AX ADC BX 0 ADD IN THE CARRY TO THE HIGH NIBB...

Page 282: ...RRUPT SOURCE SYNCHRONIZE INTERNAL REQUESTS LOW PRIORITY RELATIVE TO CHANNEL 1 BYTE XFERS MOV AX 0001011101010110B MOV DX D0CON OUT DX AX NOW WE ASSUME THAT TIMER 2 HAS BEEN PROPERLY PROGRAMMED FOR A 2...

Page 283: ......

Page 284: ...11 Math Coprocessing...

Page 285: ......

Page 286: ...ithout dependence on programmed algorithms Overall math performance exceeds that afforded by a general purpose processor and software alone For the 80C186 Modular Core family the 80C187 math coprocess...

Page 287: ...utes code written for the Intel387 DX and Intel387 SX math coprocessors The 80C187 conforms to ANSI IEEE Standard 754 1985 11 3 1 80C187 Instruction Set 80C187 instructions fall into six functional gr...

Page 288: ...uare root instruction that executes faster than ordinary division Other arithmetic instruc tions perform exact modulo division round real numbers to integers and scale values by powers of two Table 11...

Page 289: ...btraction FDIVR Divide real reversed FSUB Subtract real FDIVRP Divide real reversed and pop FSUBP Subtract real and pop FIDIVR Integer divide reversed FISUB Integer subtract Other Operations FSUBR Sub...

Page 290: ...Use prologue code to reduce arguments to a range accepted by the instruction Use epilogue code to adjust the result to the range of the original arguments The transcendentals operate on the top one o...

Page 291: ...p see Table 11 6 includes initialization excep tion handling and task switching instructions Table 11 5 80C187 Constant Instructions FLDZ Load 0 1 FLD1 Load 1 0 FLDPI Load FLDL2T Load log2 10 FLDL2E L...

Page 292: ...bit floating point numeric value Temporary real is the native 80C187 format Figure 11 1 graphically represents these data types 11 4 MICROPROCESSOR AND COPROCESSOR OPERATION The 80C187 interfaces dir...

Page 293: ...S 0 63 52 I Biased Exponent Significand S I 79 64 63 0 Biased Exponent Significand S X d 17 d 16 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 NOTES S Sign bit 0 positive 1 neg...

Page 294: ...Modular Core Family 80C187 System Configuration ALE PEREQ RESET PEREQ 80C187 CKM NPS2 80C186 Modular Core Latch D15 0 External Oscillator CLKOUT RESET WR RD NCS ERROR NPS1 CLK NPWR NPRD BUSY BUSY ERR...

Page 295: ...each data transfer between memory and the 80C187 via the mi croprocessor takes at least 17 processor clocks The microprocessor cannot process any numerics ESC opcodes alone If the CPU encounters a nu...

Page 296: ...187 access cannot activate NCS nu merics coprocessor select regardless of programming In a buffered system it is customary to place the 80C187 on the local bus Since DTR and DEN function normally duri...

Page 297: ...rtially Buffered Bus ALE PEREQ RESET PEREQ EN 80C187 CKM NPS2 80C186 Modular Core Latch D15 0 External Oscillator CLKOUT RESET WR RD CLK NPRD BUSY BUSY ERROR T OE D15 8 T OE Buffer Buffer A15 0 D7 0 E...

Page 298: ...that result as if it is valid further compounding the original error Insert the FNOP in struction at the end of the 80C187 routine to force an ERROR check If the program is written in a high level la...

Page 299: ...ia Processor Interrupt Pin INTx CLKOUT D15 0 CMD1 CMD0 PEREQ BUSY ALE A19 A16 AD15 0 RESET CKM NPS2 Q D Q D EN D15 0 A19 0 A2 A1 80C187 RESET 80C186 Modular Core BUSY PEREQ 74 74 CLK Latch ERROR NPWR...

Page 300: ...vel languages lib_80186 segment public code assume cs lib_80186 public _187_init _187_initproc far push bp save caller s bp mov bp sp get current top of stack cli disable maskable interrupts fninit in...

Page 301: ...he computation are the coordinates x and y expressed as 32 bit reals NOTES This routine is coded for Intel ASM86 It is not set up as an HLL callable routine This code assumes that the 80C187 has alrea...

Page 302: ...12 ONCE Mode...

Page 303: ......

Page 304: ...rom board log ic and essentially take over operation of the board without removing the soldered device from the board 12 1 ENTERING LEAVING ONCE MODE Forcing UCS and LCS low while RES is asserted low...

Page 305: ...2 Figure 12 1 Entering Leaving ONCE Mode RES UCS LCS All output bidirectional weakly held pins except OSCOUT NOTES 1 Entering ONCE Mode 2 Latching ONCE Mode 3 Leaving ONCE Mode assuming 2 occurred 1...

Page 306: ...A 80C186 Instruction Set Additions and Extensions...

Page 307: ......

Page 308: ...struction set Data transfer instructions PUSHA POPA String instructions INS OUTS High level instructions ENTER LEAVE BOUND A 1 1 Data Transfer Instructions PUSHA POPA PUSHA push all and POPA pop all a...

Page 309: ...reates the stack frame required by most block structured high level languages The first parameter size specifies the number of bytes of dynamic storage to be allocated for the procedure being entered...

Page 310: ...edures C and B operate at the same lexical nesting level The following is a summary of the variable access for Figure A 2 1 Main has variables at fixed locations 2 Procedure A can access only the fixe...

Page 311: ...t Level 1 After Main calls Procedure A ENTER creates a new display for Procedure A The first word points to the previous value of BP BPM The second word points to the current value of BP BPA BPM conta...

Page 312: ...Figure A 5 After Procedure B calls Procedure C ENTER creates the display for Procedure C The first word of the display points to the previous value of BP BPB The second word points to the value of BP...

Page 313: ...0C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS A 6 Figure A 5 Stack Frame for Procedure B at Level 3 Called from A A1004 0A Old BP BP SP 15 0 BPM BPM BPM Display B Dynamic Storage B BPA BPM BPA BPA BP...

Page 314: ...First LEAVE copies the current BP to the Stack Pointer releasing the stack space allocated to the current procedure Second LEAVE pops the old value of BP from the stack to return to the calling proce...

Page 315: ...s of the two signed boundary values The lower limit word is at this address and the upper limit word immediately follows The limit values cannot be register operands if they are an invalid opcode exce...

Page 316: ...ft arithmetic left shifts the destination operand left by an immediate value SAL has two operands The first destination is the effective address to be shifted The second count is an immediate byte val...

Page 317: ...ificant bit of destination rotates into the most significant bit RCL destination count RCL immediate rotate through carry left rotates the destination byte or word left by an imme diate value RCL has...

Page 318: ...B Input Synchronization...

Page 319: ......

Page 320: ...a stable state The data sheet specifies a setup and hold window larger than is actually required However variations in device operation e g temperature voltage require that a larger window be specifi...

Page 321: ...the actual size of the sampling window of the data latch and by the amount of time between the strobe sig nals of the two latches As the sampling window gets smaller the number of times an asynchro no...

Page 322: ...C Instruction Set Descriptions...

Page 323: ......

Page 324: ...ed must lie within 128 to 127 bytes of the first byte of the next instruction accum Register AX for word transfers AL for bytes port An I O port number specified as an immediate value of 0 255 or regi...

Page 325: ...ster DI short label A label within the 128 to 127 bytes of the end of the instruction near label A lavel in current code segment far label A label in another code segment near proc A procedure in curr...

Page 326: ...set maskable interrupts will cause the CPU to transfer control to an interrupt vector specified location OF Overflow Flag Set if the signed result cannot be expressed within the number of bits in the...

Page 327: ...turned in AL and the remainder is returned in AH both high order half bytes are zeroed Instruction Operands none AL AH 0AH AL AH 0 AF CF DF IF OF PF SF TF ZF AAM ASCII Adjust for Multiply AAM Corrects...

Page 328: ...tion operand with the result Both operands may be signed or unsigned binary numbers see AAA and DAA Since ADC incor porates a carry from a previous operation it can be used to write routines to add nu...

Page 329: ...to the destination operand A bit in the result is set if both corre sponding bits of the original operands are set otherwise the bit is cleared Instruction Operands AND reg reg AND reg mem AND mem re...

Page 330: ...procedure name Activates an out of line procedure saving information on the stack to permit a RET return instruction in the procedure to transfer control back to the instruction following the CALL Th...

Page 331: ...rry right RCR instructions Instruction Operands none CF 0 AF CF DF IF OF PF SF TF ZF CLD Clear Direction flag CLD Zeroes the direction flag DF causing the string instructions to auto increment the sou...

Page 332: ...erands none IF 0 AF CF DF IF OF PF SF TF ZF CMC Complement Carry Flag CMC Toggles complement carry flag CF to its opposite state and affects no other flags Instruction Operands none if CF 0 then CF 1...

Page 333: ...word from the source byte or word The destination byte or word is addressed by the destination index DI register and the source byte or word is addresses by the source index SI register CMPS updates t...

Page 334: ...F 1 if AL 9FH or CF 1 then AL AL 60H CF 1 AF CF DF IF OF PF SF TF ZF DAS Decimal Adjust for Subtraction DAS Corrects the result of a previous subtraction of two valid packed decimal operands the desti...

Page 335: ...DEC reg DEC mem dest dest 1 AF CF DF IF OF PF SF TF ZF Table C 4 Instruction Set Continued Name Description Operation Flags Affected NOTE The three symbols used in the Flags Affected column are defin...

Page 336: ...inder are undefined Nonintegral quotients are truncated to integers Instruction Operands DIV reg DIV mem When Source Operand is a Byte temp byte src if temp AX FFH then type 0 interrupt is generated S...

Page 337: ...ZF ESC Escape ESC Provides a mechanism by which other processors coprocessors may receive their instructions from the 8086 or 8088 instruction stream and make use of the 8086 or 8088 addressing modes...

Page 338: ...est on INTR if interrupts are enabled Instruction Operands none None AF CF DF IF OF PF SF TF ZF Table C 4 Instruction Set Continued Name Description Operation Flags Affected NOTE The three symbols use...

Page 339: ...e 0 interrupt is generated In particular this occurs if division by 0 is attempted Nonintegral quotients are truncated toward 0 to integers and the remainder has the same sign as the dividend Instruct...

Page 340: ...is a Word DX AX word src AX if DX sign extension of AX then CF 0 else CF 1 OF CF AF CF DF IF OF PF SF TF ZF IN Input Byte or Word IN accum port Transfers a byte or a word from an input port to the AL...

Page 341: ...cannot be overridden After the data transfer takes place the DI register increments or decrements depending on the value of the direction flag DF The DI register changes by 1 for byte transfers or 2 f...

Page 342: ...eplaces CS SP again is decremented by two and IP is pushed onto the stack and is replaced by the first word of the interrupt pointer If interrupt type 3 the assembler generates a short 1 byte form of...

Page 343: ...P CS and the flags from the stack IRET thus affects all flags by restoring them to previously saved values IRET is used to exit any interrupt procedure whether activated by hardware or software Instru...

Page 344: ...ot Above JBE disp8 JNA disp8 Transfers control to the target location if the tested condition C 1 or ZF 1 is true Instruction Operands JBE short label JNA short label if CF 1 or ZF 1 then IP IP disp8...

Page 345: ...8 Transfers control to the target location if the condition tested SF OF and ZF 0 is true Instruction Operands JG short label JNLE short label if SF OF and ZF 0 then IP IP disp8 sign ext to 16 bits AF...

Page 346: ...TF ZF JMP Jump Unconditionally JMP target Transfers control to the target location Instruction Operands JMP short label JMP near label JMP far label JMP memptr JMP regptr if Inter segment then CS SEG...

Page 347: ...location if the tested condition SF 0 is true Instruction Operands JNS short label if SF 0 then IP IP disp8 sign ext to 16 bits AF CF DF IF OF PF SF TF ZF JNP JPO Jump on Not Parity Jump on Parity Od...

Page 348: ...tion Format JS short label if SF 1 then IP IP disp8 sign ext to 16 bits AF CF DF IF OF PF SF TF ZF LAHF Load Register AH From Flags LAHF Copies SF ZF AF PF and CF the 8080 8085 flags into bits 7 6 4 2...

Page 349: ...eave LEAVE Reverses the action of the most recent ENTER instruction Collapses the last stack frame created First LEAVE copies the current BP to the stack pointer releasing the stack space allocated to...

Page 350: ...mode to assert its bus LOCK signal while the following instruction executes The instruction most useful in this context is an exchange register with memory The LOCK prefix may be combined with the seg...

Page 351: ...f CX is not 0 otherwise the instruction following LOOP is executed Instruction Operands LOOP short label CX CX 1 if CX 0 then IP IP disp8 sign ext to 16 bits AF CF DF IF OF PF SF TF ZF LOOPE LOOPZ Loo...

Page 352: ...sfers a byte or a word from the source operand to the destination operand Instruction Operands MOV mem accum MOV accum mem MOV reg reg MOV reg mem MOV mem reg MOV reg immed MOV mem immed MOV seg reg r...

Page 353: ...urce operand is a word then it is multiplied by register AX and the double length result is returned in registers DX and AX The operands are treated as unsigned binary numbers see AAM If the upper hal...

Page 354: ...dest dest 1 affecting flags AF CF DF IF OF PF SF TF ZF NOP No Operation NOP Causes the CPU to do nothing Instruction Operands none None AF CF DF IF OF PF SF TF ZF NOT Logical Not NOT dest Inverts the...

Page 355: ...AX register respec tively to an output port The port number may be specified either with an immediate byte constant allowing access to ports numbered 0 through 255 or with a number previously placed i...

Page 356: ...tion Operands OUTS port src_string OUTS repeat port src_string dst src AF CF DF IF OF PF SF TF ZF POP Pop POP dest Transfers the word at the current top of stack pointed to by SP to the destination op...

Page 357: ...then incremented by two to point to the new top of stack Instruction Operands none Flags SP 1 SP SP SP 2 AF CF DF IF OF PF SF TF ZF PUSH Push PUSH src Decrements SP by two and then transfers a word fr...

Page 358: ...P 2 SP 1 SP SI SP SP 2 SP 1 SP DI AF CF DF IF OF PF SF TF ZF PUSHF Push Flags PUSHF Decrements SP by two and then transfers all flags to the word at the top of stack pointed to by SP Instruction Opera...

Page 359: ...ined AF CF DF IF OF PF SF TF ZF RCR Rotate Through Carry Right RCR dest count Operates exactly like RCL except that the bits are rotated right instead of left Instruction Operands RCR reg n RCR mem n...

Page 360: ...n REPNE and REPNZ are mnemonics for the same prefix byte These instructions function the same as REPE and REPZ except that the zero flag must be cleared or the repetition is terminated ZF does not nee...

Page 361: ...T immed8 IP SP 1 SP SP SP 2 if inter segment then CS SP 1 SP SP SP 2 if add immed8 to SP then SP SP data AF CF DF IF OF PF SF TF ZF ROL Rotate Left ROL dest count Rotates the destination byte or word...

Page 362: ...efined AF CF DF IF OF PF SF TF ZF SAHF Store Register AH Into Flags SAHF Transfers bits 7 6 4 2 and 0 from register AH into SF ZF AF PF and CF respectively replacing whatever values these flags previo...

Page 363: ...al value Note that SAR does not produce the same result as the dividend of an equivalent IDIV instruction if the destination operand is negative and 1 bits are shifted out For example shifting 5 right...

Page 364: ...ds SBB reg reg SBB reg mem SBB mem reg SBB accum immed SBB reg immed SBB mem immed if CF 1 then dest dest src 1 else dest dest src AF CF DF IF OF PF SF TF ZF Table C 4 Instruction Set Continued Name D...

Page 365: ...eparture from a given value If SCAS is prefixed with REPNE or REPNZ the operation is interpreted as scan while not end of string CX not 0 and string element is not equal to scan value ZF 0 Instruction...

Page 366: ...then OF 1 else OF 0 else OF undefined AF CF DF IF OF PF SF TF ZF STC Set Carry Flag STC Sets CF to 1 Instruction Operands none CF 1 AF CF DF IF OF PF SF TF ZF STD Set Direction Flag STD Sets DF to 1 c...

Page 367: ...pdates DI to point to the next location in the string As a repeated operation Instruction Operands STOS dest string STOS repeat dest string When Source Operand is a Byte DEST AL if DF 0 then DI DI DEL...

Page 368: ...but does not return the result i e neither operand is changed If a TEST instruction is followed by a JNZ jump if not zero instruction the jump will be taken if there are any corresponding one bits in...

Page 369: ...semaphore that controls access to a resource shared by multiple processors Instruction Operands XCHG accum reg XCHG mem reg XCHG reg reg temp dest dest src src temp AF CF DF IF OF PF SF TF ZF Table C...

Page 370: ...tion Operands XLAT src table AL BX AL AF CF DF IF OF PF SF TF ZF XOR Exclusive Or XOR dest src Performs the logical exclusive or of the two operands and returns the result to the destination operand A...

Page 371: ......

Page 372: ...D Instruction Set Opcodes and Clock Cycles...

Page 373: ......

Page 374: ...A Calculation mod Effect on EA Calculation 0 0 0 BX SI DISP 0 0 if r m 110 DISP 0 disp low and disp high are absent 0 0 1 BX DI DISP 0 0 if r m 110 EA disp high disp low 0 1 0 BP SI DISP 0 1 DISP disp...

Page 375: ...10 segment register 0 0 0 reg 1 1 0 9 immediate 0 1 1 0 1 0 s 0 data data if s 0 10 POP Pop memory 1 0 0 0 1 1 1 1 mod 000 r m 20 register 0 1 0 1 1 reg 10 segment register 0 0 0 reg 1 1 1 reg 01 8 P...

Page 376: ...if sw 01 4 16 immediate to accumulator 0 0 0 0 0 1 0 w data data if w 1 3 4 1 ADC Add with carry reg memory with register to either 0 0 0 1 0 0 d w mod reg r m 3 10 immediate to register memory 1 0 0...

Page 377: ...0 immediate with register memory 1 0 0 0 0 0 s w mod 111 r m data data if sw 01 3 10 immediate with accumulator 0 0 1 1 1 1 0 w data data if w 1 3 4 1 AAS ASCII adjust for subtraction 0 0 1 1 1 1 1 1...

Page 378: ...m data data if w 1 4 16 immediate to accumulator 0 0 1 0 0 1 0 w data data if w 1 3 4 1 OR Or reg memory and register to either 0 0 0 0 1 0 d w mod reg r m 3 10 immediate to register memory 1 0 0 0 0...

Page 379: ...NSTRUCTIONS Continued LODS Load byte word to AL AX 1 0 1 0 1 1 0 w 12 STOS Store byte word from AL AX 1 0 1 0 1 0 1 w 10 Repeated by count in CX MOVS Move byte word 1 1 1 1 0 0 1 0 1 0 1 0 0 1 0 w 8 8...

Page 380: ...1 0 0 1 1 disp 4 13 2 JNC not carry 0 1 1 1 0 0 1 1 disp 4 13 2 JNBE JA not below or equal above 0 1 1 1 0 1 1 1 disp 4 13 2 JNP JPO not parity parity odd 0 1 1 1 1 0 1 1 disp 4 13 2 JNO not overflow...

Page 381: ...1 1 0 0 0 1 0 disp 6 16 2 LOOPZ LOOPE Loop while zero equal 1 1 1 0 0 0 0 1 disp 5 16 2 LOOPNZ LOOPNE Loop while not zero not equal 1 1 1 0 0 0 0 0 disp 5 16 2 JCXZ Jump if CX zero 1 1 1 0 0 0 1 1 dis...

Page 382: ...ytes 3 6 ASM 86 Instruction Format Hex Binary 00 0000 0000 mod reg r m disp lo disp hi add reg8 mem8 reg8 01 0000 0001 mod reg r m disp lo disp hi add reg16 mem16 reg16 02 0000 0010 mod reg r m disp l...

Page 383: ...eg r m disp lo disp hi sbb reg8 reg8 mem8 1B 0001 1011 mod reg r m disp lo disp hi sbb reg16 reg16 mem16 1C 0001 1100 data 8 sbb AL immed8 1D 0001 1101 data lo data hi sbb AX immed16 1E 0001 1110 push...

Page 384: ...hi xor reg16 mem16 reg16 3A 0011 1010 mod reg r m disp lo disp hi xor reg8 reg8 mem8 3B 0011 1011 mod reg r m disp lo disp hi xor reg16 reg16 mem16 3C 0011 1100 data 8 xor AL immed8 3D 0011 1101 data...

Page 385: ...m data lo data hi imul immed16 70 0111 0000 IP inc 8 jo short label 71 0111 0001 IP inc 8 jno short label 72 0111 0010 IP inc 8 jb jnae jc short label 73 0111 0011 IP inc 8 jnb jae jnc short label 74...

Page 386: ...disp lo disp hi data lo data hi sub reg16 mem16 immed16 mod 110 r m disp lo disp hi data lo data hi xor reg16 mem16 immed16 mod 111 r m disp lo disp hi data lo data hi cmp reg16 mem16 immed16 82 1000...

Page 387: ...1001 0010 xchg AX DX 93 1001 0011 xchg AX BX 94 1001 0100 xchg AX SP 95 1001 0101 xchg AX BP 96 1001 0110 xchg AX SI 97 1001 0111 xchg AX DI 98 1001 1000 cbw 99 1001 1001 cwd 9A 1001 1010 disp lo dis...

Page 388: ...100 data lo data hi mov SP immed16 BD 1011 1101 data lo data hi mov BP immed16 BE 1011 1110 data lo data hi mov SI immed16 BF 1011 1111 data lo data hi mov DI immed16 C0 1100 0000 mod 000 r m data 8 r...

Page 389: ...1 r m mod 100 r m mod 101 r m mod 110 r m mod 111 r m C8 1100 1000 data lo data hi level enter immed16 immed8 C9 1100 1001 leave CA 1100 1010 data lo data hi ret immed16 intersegment CB 1100 1011 ret...

Page 390: ...m disp lo disp hi ror reg16 mem16 CL mod 010 r m disp lo disp hi rcl reg16 mem16 CL mod 011 r m disp lo disp hi rcr reg16 mem16 CL mod 100 r m disp lo disp hi sal shl reg16 mem16 CL mod 101 r m disp...

Page 391: ...p repe repz F4 1111 0100 hlt F5 1111 0101 cmc F6 1111 0110 mod 000 r m disp lo disp hi data 8 test reg8 mem8 immed8 mod 001 r m mod 010 r m disp lo disp hi not reg8 mem8 mod 011 r m disp lo disp hi ne...

Page 392: ...mod 110 r m mod 111 r m FF 1111 1111 mod 000 r m disp lo disp hi inc mem16 mod 001 r m disp lo disp hi dec mem16 mod 010 r m disp lo disp hi call reg16 mem16 intrasegment mod 011 r m disp lo disp hi c...

Page 393: ...H SP PUSH BP PUSH SI PUSH DI 6x PUSHA POPA BOUND w f r m 7x JO JNO JB JNAE JC JNB JAE JNC JE JZ JNE JNZ JBE JNA JNBE JA 8x Immed b r m Immed w r m Immed b r m Immed is r m TEST b r m TEST w r m XCHG b...

Page 394: ...BX POP SP POP BP POP SI POP DI 5x PUSH w i IMUL w i PUSH b i IMUL w i INS b INS w OUTS b OUTS w 6x JS JNS JP JPE JNP JPO JL JNGE JNL JGE JLE JNG JNLE JG 7x MOV b f r m MOV w f r m MOV b t r m MOV w t...

Page 395: ...PU register is immediate byte sign extended si short intrasegment w word operation i immediate l long intersegment sr segment register z zero Byte 2 Immed Shift Grp1 Grp2 mod 000 r m ADD ROL TEST INC...

Page 396: ...Index...

Page 397: ......

Page 398: ...les Data transfers Address bus See Address and data bus Address space See Memory space I O space Addressing modes 2 27 2 36 and string instructions 2 34 based 2 30 2 31 2 32 based index 2 34 2 35 dire...

Page 399: ...A 10 8 and DMA acknowledge signal 10 22 and HALT bus cycles 3 28 and READY 6 15 6 16 and wait states 6 15 6 16 block diagram 6 3 bus cycle decoding 6 17 examples 6 18 6 22 features and benefits 6 1 fu...

Page 400: ...gramming pointers 10 10 10 14 requests 10 3 external 10 4 internal 10 6 software 10 6 Timer 2 10 6 selecting source 10 17 synchronization destination synchronized 10 5 selecting 10 18 source synchroni...

Page 401: ...ns A 9 string instructions 2 22 2 23 A 2 INT instruction single byte See Breakpoint interrupt INT0 instruction 2 44 INTA bus cycle See Bus cycles Integer defined 2 37 10 7 Interrupt Control register 8...

Page 402: ...2 8 accessing 2 5 2 10 2 11 2 13 address base value 2 10 2 11 2 12 Effective Address EA 2 13 logical 2 10 2 12 offset value 2 10 2 13 overriding 2 11 2 13 physical 2 3 2 10 2 12 and dynamic code reloc...

Page 403: ...13 3 18 implementation approaches 3 13 timing concerns 3 17 Real defined 10 7 Real time clock code example 9 17 9 20 Refresh address 7 4 Refresh Base Address Register RFBASE 7 8 Refresh bus cycle See...

Page 404: ...T Technical support 1 6 Temporary real defined 10 7 Terminology above vs greater 2 26 below vs less 2 26 device names 1 2 Timer Control Registers TxCON 9 7 9 8 Timer Count Registers TxCNT 9 10 Timer C...

Page 405: ...INDEX Index 8 and PCB accesses 4 4 and READY input 3 13 Word integer defined 10 7 World Wide Web 1 6 Write bus cycle 3 22 Z Zero Flag ZF 2 7 2 9 2 23...

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