Intel 80C186XL, User Manual

Page: 86 / 405

3-5
BUS INTERFACE UNIT
Figure 3-4. 16-Bit Data Bus Odd Word Transfers
3.2.2 8-Bit Data Bus
The memory address space on an 8-bit data bus is physically implemented as one bank of 1 Mbyte
(see Figure 3-1 on page 3-2). Address lines A19:0 select a specific byte within the bank. Unlike
transfers with a 16-bit bus, byte and word transfers (to even or odd addresses) all transfer data
over the same 8-bit bus.
Byte transfers to even or odd addresses transfer information in one bus cycle. Word transfers to
even or odd addresses transfer information in two bus cycles. The BIU automatically converts the
word access into two consecutive byte accesses, making the operation transparent to the program-
mer.
A1108-0A
Second Bus Cycle
A19:1 D15:8 D7:0 A0
(High)
BHE
(Low)
Y
X
(X + 1)
A19:1 D15:8 D7:0
A0
(Low)
BHE
(High)
(Y)
X
X + 1
First Bus Cycle
Y + 1