C-5
INSTRUCTION SET DESCRIPTIONS
AAS
ASCII Adjust for Subtraction:
AAS
Corrects the result of a previous
subtraction of two valid unpacked
decimal operands (the destination
operand must have been specified as
register AL). Changes the content of
AL to a valid unpacked decimal
number; the high-order half-byte is
zeroed.
Instruction Operands:
none
if
((AL) and 0FH) > 9 or (AF) = 1
then
(AL)
←
(AL) – 6
(AH)
←
(AH) – 1
(AF)
←
1
(CF)
←
(AF)
(AL)
←
(AL) and 0FH
AF
ü
CF
ü
DF –
IF –
OF ?
PF ?
SF ?
TF –
ZF ?
ADC
Add with Carry:
ADC dest, src
Sums the operands, which may be
bytes or words, adds one if CF is set
and replaces the destination operand
with the result. Both operands may be
signed or unsigned binary numbers
(see AAA and DAA). Since ADC incor-
porates a carry from a previous
operation, it can be used to write
routines to add numbers longer than
16 bits.
Instruction Operands:
ADC reg, reg
ADC reg, mem
ADC mem, reg
ADC reg, immed
ADC mem, immed
ADC accum, immed
if
(CF) = 1
then
(dest)
←
(dest) + (src) + 1
else
(dest)
←
(dest) + (src)
AF
ü
CF
ü
DF –
IF –
OF
ü
PF
ü
SF
ü
TF –
ZF
ü
Table C-4. Instruction Set (Continued)
Name
Description
Operation
Flags
Affected
NOTE:
The three symbols used in the Flags Affected column are defined as follows:
– the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
ü
the flag is updated after the instruction is executed
Summary of Contents for 80C186XL
Page 1: ...80C186XL 80C188XL Microprocessor User s Manual...
Page 2: ...80C186XL 80C188XL Microprocessor User s Manual 1995...
Page 18: ...1 Introduction...
Page 19: ......
Page 27: ......
Page 28: ...2 Overview of the 80C186 Family Architecture...
Page 29: ......
Page 79: ......
Page 80: ...3 Bus Interface Unit...
Page 81: ......
Page 127: ......
Page 128: ...4 Peripheral Control Block...
Page 129: ......
Page 137: ......
Page 138: ...5 ClockGenerationand Power Management...
Page 139: ......
Page 154: ...6 Chip Select Unit...
Page 155: ......
Page 178: ...7 Refresh Control Unit...
Page 179: ......
Page 193: ......
Page 194: ...8 Interrupt Control Unit...
Page 195: ......
Page 227: ......
Page 228: ...9 Timer Counter Unit...
Page 229: ......
Page 253: ......
Page 254: ...10 Direct Memory Access Unit...
Page 255: ......
Page 283: ......
Page 284: ...11 Math Coprocessing...
Page 285: ......
Page 302: ...12 ONCE Mode...
Page 303: ......
Page 306: ...A 80C186 Instruction Set Additions and Extensions...
Page 307: ......
Page 318: ...B Input Synchronization...
Page 319: ......
Page 322: ...C Instruction Set Descriptions...
Page 323: ......
Page 371: ......
Page 372: ...D Instruction Set Opcodes and Clock Cycles...
Page 373: ......
Page 396: ...Index...
Page 397: ......