OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2-24
Unconditional transfer instructions can transfer control either to a target instruction within the
current code segment (intrasegment transfer) or to a different code segment (intersegment trans-
fer). The assembler terms an intrasegment transfer SHORT or NEAR and an intersegment trans-
fer FAR. The transfer is made unconditionally when the instruction is executed. CALL, RET and
JMP are all unconditional transfers.
CALL is used to transfer the program to a procedure. A CALL can be NEAR or FAR. A NEAR
CALL stacks only the Instruction Pointer, while a FAR CALL stacks both the Instruction Pointer
and the Code Segment register. The RET instruction uses the information pushed onto the stack
to determine where to return when the procedure finishes. Note that the RET and CALL instruc-
tions must be the same type. This can be a problem when the CALL and RET instructions are in
separately assembled programs. The JMP instruction does not push any information onto the
stack. A JMP instruction can be NEAR or FAR.
Conditional transfer instructions are jumps that may or may not transfer control, depending on
the state of the CPU flags when the instruction is executed. Each conditional transfer instruction
tests a different combination of flags for a condition (see Table 2-10). If the condition is logically
TRUE, control is transferred to the target specified in the instruction. If the condition is FALSE,
control passes to the instruction following the conditional jump. All conditional jumps are
SHORT. The target must be in the current code segment within –128 to +127 bytes of the next
instruction’s first byte. For example, JMP 00H causes a jump to the first byte of the next instruc-
tion. Jumps are made by adding the relative displacement of the target to the Instruction Pointer.
All conditional jumps are self-relative and are appropriate for position-independent routines.
Summary of Contents for 80C186XL
Page 1: ...80C186XL 80C188XL Microprocessor User s Manual...
Page 2: ...80C186XL 80C188XL Microprocessor User s Manual 1995...
Page 18: ...1 Introduction...
Page 19: ......
Page 27: ......
Page 28: ...2 Overview of the 80C186 Family Architecture...
Page 29: ......
Page 79: ......
Page 80: ...3 Bus Interface Unit...
Page 81: ......
Page 127: ......
Page 128: ...4 Peripheral Control Block...
Page 129: ......
Page 137: ......
Page 138: ...5 ClockGenerationand Power Management...
Page 139: ......
Page 154: ...6 Chip Select Unit...
Page 155: ......
Page 178: ...7 Refresh Control Unit...
Page 179: ......
Page 193: ......
Page 194: ...8 Interrupt Control Unit...
Page 195: ......
Page 227: ......
Page 228: ...9 Timer Counter Unit...
Page 229: ......
Page 253: ......
Page 254: ...10 Direct Memory Access Unit...
Page 255: ......
Page 283: ......
Page 284: ...11 Math Coprocessing...
Page 285: ......
Page 302: ...12 ONCE Mode...
Page 303: ......
Page 306: ...A 80C186 Instruction Set Additions and Extensions...
Page 307: ......
Page 318: ...B Input Synchronization...
Page 319: ......
Page 322: ...C Instruction Set Descriptions...
Page 323: ......
Page 371: ......
Page 372: ...D Instruction Set Opcodes and Clock Cycles...
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Page 396: ...Index...
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