INSTRUCTION SET DESCRIPTIONS
C-10
CMP
Compare:
CMP
dest, src
Subtracts the source from the desti-
nation, which may be bytes or words,
but does not return the result. The
operands are unchanged, but the flags
are updated and can be tested by a
subsequent conditional jump
instruction. The comparison reflected
in the flags is that of the destination to
the source. If a CMP instruction is
followed by a JG (jump if greater)
instruction, for example, the jump is
taken if the destination operand is
greater than the source operand.
Instruction Operands:
CMP reg, reg
CMP reg, mem
CMP mem, reg
CMP reg, immed
CMP mem, immed
CMP accum, immed
(dest) – (src)
AF
ü
CF
ü
DF –
IF –
OF
ü
PF
ü
SF
ü
TF –
ZF
ü
CMPS
Compare String:
CMPS dest-string, src-string
Subtracts the destination byte or word
from the source byte or word. The
destination byte or word is addressed
by the destination index (DI) register
and the source byte or word is
addresses by the source index (SI)
register. CMPS updates the flags to
reflect the relationship of the
destination element to the source
element but does not alter either
operand and updates SI and DI to
point to the next string element.
Instruction Operands:
CMP dest-string, src-string
CMP (repeat) dest-string, src-string
(dest-string) – (src-string)
if
(DF) = 0
then
(SI)
←
(SI) + DELTA
(DI)
←
(DI) + DELTA
else
(SI)
←
(SI) – DELTA
(DI)
←
(DI) – DELTA
AF
ü
CF
ü
DF –
IF –
OF
ü
PF
ü
SF
ü
TF –
ZF
ü
Table C-4. Instruction Set (Continued)
Name
Description
Operation
Flags
Affected
NOTE:
The three symbols used in the Flags Affected column are defined as follows:
– the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
ü
the flag is updated after the instruction is executed
Summary of Contents for 80C186XL
Page 1: ...80C186XL 80C188XL Microprocessor User s Manual...
Page 2: ...80C186XL 80C188XL Microprocessor User s Manual 1995...
Page 18: ...1 Introduction...
Page 19: ......
Page 27: ......
Page 28: ...2 Overview of the 80C186 Family Architecture...
Page 29: ......
Page 79: ......
Page 80: ...3 Bus Interface Unit...
Page 81: ......
Page 127: ......
Page 128: ...4 Peripheral Control Block...
Page 129: ......
Page 137: ......
Page 138: ...5 ClockGenerationand Power Management...
Page 139: ......
Page 154: ...6 Chip Select Unit...
Page 155: ......
Page 178: ...7 Refresh Control Unit...
Page 179: ......
Page 193: ......
Page 194: ...8 Interrupt Control Unit...
Page 195: ......
Page 227: ......
Page 228: ...9 Timer Counter Unit...
Page 229: ......
Page 253: ......
Page 254: ...10 Direct Memory Access Unit...
Page 255: ......
Page 283: ......
Page 284: ...11 Math Coprocessing...
Page 285: ......
Page 302: ...12 ONCE Mode...
Page 303: ......
Page 306: ...A 80C186 Instruction Set Additions and Extensions...
Page 307: ......
Page 318: ...B Input Synchronization...
Page 319: ......
Page 322: ...C Instruction Set Descriptions...
Page 323: ......
Page 371: ......
Page 372: ...D Instruction Set Opcodes and Clock Cycles...
Page 373: ......
Page 396: ...Index...
Page 397: ......