Intel 80C186XL, User Manual

Page: 273 / 405

DIRECT MEMORY ACCESS UNIT
10-18
10.2.1.4 Arming the DMA Channel
Each DMA channel must be armed before it can recognize DMA requests. A channel is armed
by setting its STRT (Start) bit in the DMA Control Register (Figure 10-11 on page 10-15). The
STRT bit can be modified only if the CHG (Change Start) bit is set at the same time. The CHG
bit is a safeguard to prevent accidentally arming a DMA channel while modifying other channel
parameters.
A DMA channel is disarmed by clearing its STRT bit. The STRT bit is cleared either directly by
software or by the channel itself when it is programmed to terminate on terminal count.
10.2.1.5 Selecting Channel Synchronization
The synchronization method for a channel is controlled by the SYN1:0 bits in the DMA Control
Register (Figure 10-11 on page 10-15).
NOTE
The combination SYN1:0=11 is reserved and will result in unpredictable
operation. When IDRQ is set (internal requests selected) the channel must
always be programmed for source-synchronized transfers (SYN1:0=01).
When programmed for unsynchronized transfers (SYN1:0=00), the DMA channel will begin to
transfer data as soon as the STRT bit is set.
10.2.1.6 Programming the Transfer Count Options
The Transfer Count Register (Figure 10-12) and the TC bit in the DMA Control Register (Figure
10-11 on page 10-15) are used to stop DMA transfers for a channel after a specified number of
transfers have occurred.
The transfer count (the number of transfers desired) is written to the DMA Transfer Count Reg-
ister. The Transfer Count Register is 16 bits wide, limiting the total number of transfers for a
channel to 65,536 (without reprogramming). The Transfer Count Register is decremented by one
after each transfer (for both byte and word transfers).