3-41
BUS INTERFACE UNIT
The major factors that influence bus latency are listed below (in order from longest delay to short-
est delay).
1.
Bus Not Ready — As long as the bus remains not ready, a bus hold request cannot be
serviced.
2.
Locked Bus Cycle — As long as LOCK remains asserted, a bus hold request cannot be
serviced. Performing a locked move string operation can take several thousands of clocks.
3.
Completion of Current Bus Cycle — A bus hold request cannot be serviced until the
current bus cycle completes. A bus hold request will not separate bus cycles required to
move odd-aligned word data. Also, bus cycles with long wait states will delay the
servicing of a bus hold request.
4.
Interrupt Acknowledge Bus Cycle — A bus hold request is not serviced until after an
INTA bus cycle has completed. An INTA bus cycle drives LOCK active.
5.
DMA and Refresh Bus Cycles — A bus hold request is not serviced until after the DMA
request or refresh bus cycle has completed. Refresh bus cycles have a higher priority than
hold bus requests. A bus hold request cannot separate the bus cycles associated with a
DMA transfer (worst case is an odd-aligned transfer, which takes four bus cycles to
complete).
3.7.1.2
Refresh Operation During a Bus HOLD
Under normal operating conditions, once HLDA has been asserted it remains asserted until
HOLD is removed. However, when a refresh bus request is generated, the HLDA output is re-
moved (driven low) to signal the need for the BIU to regain control of the local bus. The BIU does
not gain control of the bus until HOLD is removed. This procedure prevents the BIU from just
arbitrarily regaining control of the bus.
Figure 3-35 shows the timing associated with the occurrence of a refresh request while HLDA is
active. Note that HLDA can be as short as one clock in duration. This happens when a refresh
request occurs just after HLDA is granted. A refresh request has higher priority than a bus hold
request; therefore, when the two occur simultaneously, the refresh request occurs before HLDA
becomes active.
Summary of Contents for 80C186XL
Page 1: ...80C186XL 80C188XL Microprocessor User s Manual...
Page 2: ...80C186XL 80C188XL Microprocessor User s Manual 1995...
Page 18: ...1 Introduction...
Page 19: ......
Page 27: ......
Page 28: ...2 Overview of the 80C186 Family Architecture...
Page 29: ......
Page 79: ......
Page 80: ...3 Bus Interface Unit...
Page 81: ......
Page 127: ......
Page 128: ...4 Peripheral Control Block...
Page 129: ......
Page 137: ......
Page 138: ...5 ClockGenerationand Power Management...
Page 139: ......
Page 154: ...6 Chip Select Unit...
Page 155: ......
Page 178: ...7 Refresh Control Unit...
Page 179: ......
Page 193: ......
Page 194: ...8 Interrupt Control Unit...
Page 195: ......
Page 227: ......
Page 228: ...9 Timer Counter Unit...
Page 229: ......
Page 253: ......
Page 254: ...10 Direct Memory Access Unit...
Page 255: ......
Page 283: ......
Page 284: ...11 Math Coprocessing...
Page 285: ......
Page 302: ...12 ONCE Mode...
Page 303: ......
Page 306: ...A 80C186 Instruction Set Additions and Extensions...
Page 307: ......
Page 318: ...B Input Synchronization...
Page 319: ......
Page 322: ...C Instruction Set Descriptions...
Page 323: ......
Page 371: ......
Page 372: ...D Instruction Set Opcodes and Clock Cycles...
Page 373: ......
Page 396: ...Index...
Page 397: ......