2-21
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2.2.1.3
Bit Manipulation Instructions
There are three groups of instructions for manipulating bits within bytes and words. These three
groups are logical, shifts and rotates. Table 2-6 lists the bit manipulation instructions and their
functions.
Logical instructions include the Boolean operators NOT, AND, OR and exclusive OR (XOR), as
well as a TEST instruction. The TEST instruction sets the flags as a result of a Boolean AND op-
eration but does not alter either of its operands.
Individual bits in bytes and words can be shifted either arithmetically or logically. Up to 32 shifts
can be performed, according to the value of the count operand coded in the instruction. The count
can be specified as an immediate value or as a variable in the CL register. This allows the shift
count to be a supplied at execution time. Arithmetic shifts can be used to multiply and divide bi-
nary numbers by powers of two. Logical shifts can be used to isolate bits in bytes or words.
Table 2-5. Arithmetic Interpretation of 8-Bit Numbers
Hex
Bit Pattern
Unsigned
Binary
Signed
Binary
Unpacked
Decimal
Packed
Decimal
07
0 0 0 0 0 1 1 1
7
+7
7
7
89
1 0 0 0 1 0 0 1
137
–119
invalid
89
C5
1 1 0 0 0 1 0 1
197
–59
invalid
invalid
Table 2-6. Bit Manipulation Instructions
Logicals
NOT
“Not” byte or word
AND
“And” byte or word
OR
“Inclusive or” byte or word
XOR
“Exclusive or” byte or word
TEST
“Test” byte or word
Shifts
SHL/SAL
Shift logical/arithmetic left byte or word
SHR
Shift logical right byte or word
SAR
Shift arithmetic right byte or word
Rotates
ROL
Rotate left byte or word
ROR
Rotate right byte or word
RCL
Rotate through carry left byte or word
RCR
Rotate through carry right byte or word
Summary of Contents for 80C186XL
Page 1: ...80C186XL 80C188XL Microprocessor User s Manual...
Page 2: ...80C186XL 80C188XL Microprocessor User s Manual 1995...
Page 18: ...1 Introduction...
Page 19: ......
Page 27: ......
Page 28: ...2 Overview of the 80C186 Family Architecture...
Page 29: ......
Page 79: ......
Page 80: ...3 Bus Interface Unit...
Page 81: ......
Page 127: ......
Page 128: ...4 Peripheral Control Block...
Page 129: ......
Page 137: ......
Page 138: ...5 ClockGenerationand Power Management...
Page 139: ......
Page 154: ...6 Chip Select Unit...
Page 155: ......
Page 178: ...7 Refresh Control Unit...
Page 179: ......
Page 193: ......
Page 194: ...8 Interrupt Control Unit...
Page 195: ......
Page 227: ......
Page 228: ...9 Timer Counter Unit...
Page 229: ......
Page 253: ......
Page 254: ...10 Direct Memory Access Unit...
Page 255: ......
Page 283: ......
Page 284: ...11 Math Coprocessing...
Page 285: ......
Page 302: ...12 ONCE Mode...
Page 303: ......
Page 306: ...A 80C186 Instruction Set Additions and Extensions...
Page 307: ......
Page 318: ...B Input Synchronization...
Page 319: ......
Page 322: ...C Instruction Set Descriptions...
Page 323: ......
Page 371: ......
Page 372: ...D Instruction Set Opcodes and Clock Cycles...
Page 373: ......
Page 396: ...Index...
Page 397: ......