INTERRUPT CONTROL UNIT
8-8
Figure 8-2. Using External 8259A Modules in Cascade Mode
8.3.3.1
Special Fully Nested Mode
Special fully nested mode is an optional feature normally used with cascade mode. It is applicable
only to INT0 and INT1. In special fully nested mode, an interrupt request is serviced even if its
In-Service bit is set.
In cascade mode, an 8259A controls up to eight external interrupts that share a single interrupt
input pin. Special fully nested mode allows the 8259A’s priority structure to be maintained. For
example, assume that the CPU is servicing a low-priority interrupt from the 8259A. While the
interrupt handler is executing, the 8259A receives a higher priority interrupt from one of its sourc-
es. The 8259A applies its own priority criteria to that interrupt and asserts its interrupt to the In-
terrupt Control Unit. Special fully nested mode allows the higher priority interrupt to be serviced
even though the In-Service bit for that source is already set. A higher priority interrupt has pre-
empted a lower priority interrupt, and interrupt nesting is fully maintained.
Special fully nested mode can also be used without cascade mode. In this case, it allows a single
external interrupt pin (either INT0 or INT1) to preempt itself.
8259A
or
82C59A
INT
INTA
8259A
or
82C59A
INT
INTA
INT0
INTA0
INT1
INTA1
Interrupt
Control
Unit
VCC
VCC
A1211-A0
Summary of Contents for 80C186XL
Page 1: ...80C186XL 80C188XL Microprocessor User s Manual...
Page 2: ...80C186XL 80C188XL Microprocessor User s Manual 1995...
Page 18: ...1 Introduction...
Page 19: ......
Page 27: ......
Page 28: ...2 Overview of the 80C186 Family Architecture...
Page 29: ......
Page 79: ......
Page 80: ...3 Bus Interface Unit...
Page 81: ......
Page 127: ......
Page 128: ...4 Peripheral Control Block...
Page 129: ......
Page 137: ......
Page 138: ...5 ClockGenerationand Power Management...
Page 139: ......
Page 154: ...6 Chip Select Unit...
Page 155: ......
Page 178: ...7 Refresh Control Unit...
Page 179: ......
Page 193: ......
Page 194: ...8 Interrupt Control Unit...
Page 195: ......
Page 227: ......
Page 228: ...9 Timer Counter Unit...
Page 229: ......
Page 253: ......
Page 254: ...10 Direct Memory Access Unit...
Page 255: ......
Page 283: ......
Page 284: ...11 Math Coprocessing...
Page 285: ......
Page 302: ...12 ONCE Mode...
Page 303: ......
Page 306: ...A 80C186 Instruction Set Additions and Extensions...
Page 307: ......
Page 318: ...B Input Synchronization...
Page 319: ......
Page 322: ...C Instruction Set Descriptions...
Page 323: ......
Page 371: ......
Page 372: ...D Instruction Set Opcodes and Clock Cycles...
Page 373: ......
Page 396: ...Index...
Page 397: ......