Intel 80C186XL, User Manual

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OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2.3.1.2 Maskable Interrupts
Maskable interrupts are the most common way to service external hardware interrupts. Software
can globally enable or disable maskable interrupts. This is done by setting or clearing the Inter-
rupt Enable bit in the Processor Status Word.
The Interrupt Control Unit processes the multiple sources of maskable interrupts and presents
them to the core via a single maskable interrupt input. The Interrupt Control Unit provides the
interrupt vector type to the 80C186 Modular Core. The Interrupt Control Unit differs among
members of the 80C186 Modular Core family; see Chapter 8, “Interrupt Control Unit,” for infor-
mation.
2.3.1.3 Exceptions
Exceptions occur when an unusual condition prevents further instruction processing until the ex-
ception is corrected. The CPU handles software interrupts and exceptions in the same way. The
interrupt type for an exception is either predefined or supplied by the instruction.
Exceptions are classified as either faults or traps, depending on when the exception is detected
and whether the instruction that caused the exception can be restarted. Faults are detected and ser-
viced before the faulting instruction can be executed. The return address pushed onto the stack
in the interrupt processing instruction points to the beginning of the faulting instruction. This al-
lows the instruction to be restarted. Traps are detected and serviced immediately after the instruc-
tion that caused the trap. The return address pushed onto the stack during the interrupt processing
points to the instruction following the trapping instruction.
Divide Error — Type 0
A Divide Error trap is invoked when the quotient of an attempted division exceeds the maximum
value of the destination. A divide-by-zero is a common example.
Single Step — Type 1
The Single Step trap occurs after the CPU executes one instruction with the Trap Flag (TF) bit set
in the Processor Status Word. This allows programs to execute one instruction at a time. Inter-
rupts are not generated after prefix instructions (e.g., REP), after instructions that modify segment
registers (e.g., POP DS) or after the WAIT instruction. Vectoring to the single-step interrupt ser-
vice routine clears the Trap Flag bit. An IRET instruction in the interrupt service routine restores
the Trap Flag bit to logic “1” and transfers control to the next instruction to be single-stepped.