INSTRUCTION SET DESCRIPTIONS
C-28
LODS
Load String (Byte or Word):
LODS
src-string
Transfers the byte or word string
element addressed by SI to register AL
or AX and updates SI to point to the
next element in the string. This
instruction is not ordinarily repeated
since the accumulator would be
overwritten by each repetition, and
only the last element would be
retained.
Instruction Operands:
LODS src-string
LODS (repeat) src-string
When Source Operand is a Byte:
(AL)
←
(src-string)
if
(DF) = 0
then
(SI)
←
(SI) + DELTA
else
(SI)
←
(SI) – DELTA
When Source Operand is a Word:
(AX)
←
(src-string)
if
(DF) = 0
then
(SI)
←
(SI) + DELTA
else
(SI)
←
(SI) – DELTA
AF –
CF –
DF –
IF –
OF –
PF –
SF –
TF –
ZF –
LOOP
Loop:
LOOP disp8
Decrements CX by 1 and transfers
control to the target location if CX is
not 0; otherwise the instruction
following LOOP is executed.
Instruction Operands:
LOOP short-label
(CX)
←
(CX) – 1
if
(CX)
≠
0
then
(IP)
←
(IP) + disp8 (sign-ext to 16 bits)
AF –
CF –
DF –
IF –
OF –
PF –
SF –
TF –
ZF –
LOOPE
LOOPZ
Loop While Equal:
Loop While Zero:
LOOPE disp8
LOOPZ
disp8
Decrements CX by 1 and transfers
control is to the target location if CX is
not 0 and if ZF is set; otherwise the
next sequential instruction is executed.
Instruction Operands:
LOOPE short-label
LOOPZ short-label
(CX)
←
(CX) – 1
if
(ZF) = 1 and (CX)
≠
0
then
(IP)
←
(IP) + disp8 (sign-ext to 16 bits)
AF –
CF –
DF –
IF –
OF –
PF –
SF –
TF –
ZF –
Table C-4. Instruction Set (Continued)
Name
Description
Operation
Flags
Affected
NOTE:
The three symbols used in the Flags Affected column are defined as follows:
– the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
ü
the flag is updated after the instruction is executed
Summary of Contents for 80C186XL
Page 1: ...80C186XL 80C188XL Microprocessor User s Manual...
Page 2: ...80C186XL 80C188XL Microprocessor User s Manual 1995...
Page 18: ...1 Introduction...
Page 19: ......
Page 27: ......
Page 28: ...2 Overview of the 80C186 Family Architecture...
Page 29: ......
Page 79: ......
Page 80: ...3 Bus Interface Unit...
Page 81: ......
Page 127: ......
Page 128: ...4 Peripheral Control Block...
Page 129: ......
Page 137: ......
Page 138: ...5 ClockGenerationand Power Management...
Page 139: ......
Page 154: ...6 Chip Select Unit...
Page 155: ......
Page 178: ...7 Refresh Control Unit...
Page 179: ......
Page 193: ......
Page 194: ...8 Interrupt Control Unit...
Page 195: ......
Page 227: ......
Page 228: ...9 Timer Counter Unit...
Page 229: ......
Page 253: ......
Page 254: ...10 Direct Memory Access Unit...
Page 255: ......
Page 283: ......
Page 284: ...11 Math Coprocessing...
Page 285: ......
Page 302: ...12 ONCE Mode...
Page 303: ......
Page 306: ...A 80C186 Instruction Set Additions and Extensions...
Page 307: ......
Page 318: ...B Input Synchronization...
Page 319: ......
Page 322: ...C Instruction Set Descriptions...
Page 323: ......
Page 371: ......
Page 372: ...D Instruction Set Opcodes and Clock Cycles...
Page 373: ......
Page 396: ...Index...
Page 397: ......