Intel 80C186XL, User Manual

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REFRESH CONTROL UNIT
7-4
The BIU does not queue DRAM refresh requests. If the Refresh Control Unit generates another
request before the BIU handles the present request, the BIU loses the present request. However,
the address associated with the request is not lost. The refresh address changes only after the BIU
runs a refresh bus cycle. If a DRAM refresh cycle is excessively delayed, there is still a chance
that the processor will successfully refresh the corresponding row of cells in the DRAM, retaining
the data.
7.4 REFRESH ADDRESSES
Figure 7-3 shows the physical address generated during a refresh bus cycle. This figure applies
to both the 8-bit and 16-bit data bus microprocessor versions. Refresh address bits RA19:13 come
from the Refresh Base Address Register. (See “Refresh Base Address Register” on page 7-8.)
Figure 7-3. Refresh Address Formation
Refresh address bits RA12:10 are always zero. A linear-feedback shift counter generates address
bits RA9:1 and RA0 is always one. The counter does not count linearly from 0 through 1FFH.
However, the counting algorithm cycles uniquely through all possible 9-bit values. It matters only
that each row of DRAM memory cells is refreshed at a specific interval. The order of the rows is
unimportant.
Address bit A0 is fixed at one during all refresh operations. In applications based on a 16-bit data
bus processor, A0 typically selects memory devices placed on the low (even) half of the bus. Ap-
plications based on an 8-bit data bus processor typically use A0 as a true address bit. The DRAM
controller must not route A0 to row address pins on the DRAMs.
20-Bit Refresh Address
0
19
From Refresh Base
Address Register From Refresh Address Counter Fixed
RA
19
RA
18
RA
17
RA
16
RA
15
RA
14
RA
13
0 0 0 RA
9
RA
8
RA
7
RA
6
RA
5
RA
4
RA
3
RA
2
RA
1
1
Fixed
A1502-0A