Intel 80C186XL, User Manual

Page: 181 / 405

REFRESH CONTROL UNIT
7-2
7.1 THE ROLE OF THE REFRESH CONTROL UNIT
Like a DMA controller, the Refresh Control Unit runs bus cycles independent of CPU execution.
Unlike a DMA controller, however, the Refresh Control Unit does not run bus cycle bursts nor
does it transfer data. The DRAM refresh process freshens individual DRAM rows in “dummy
read” cycles, while cycling through all necessary addresses.
The microprocessor interface to DRAMs is more complicated than other memory interfaces. A
complete DRAM controller requires circuitry beyond that provided by the processor even in the
simplest configurations. This circuitry must respond correctly to reads, writes and DRAM refresh
cycles. The external DRAM controller generates the Row Address Strobe (RAS), Column Ad-
dress Strobe (CAS) and other DRAM control signals.
Pseudo-static RAMs use dynamic memory cells but generate address strobes and refresh address-
es internally. The address counters still need external timing pulses. These pulses are easy to de-
rive from the processor’s bus control signals. Pseudo-static RAMs do not need a full DRAM
controller.
7.2 REFRESH CONTROL UNIT CAPABILITIES
A 9-bit address counter forms the refresh addresses, supporting any dynamic memory devices
with up to 9 rows of memory cells (9 refresh address bits). This includes all practical DRAM sizes
for the processor’s 1 Mbyte address space.
7.3 REFRESH CONTROL UNIT OPERATION
Figure 7-2 illustrates Refresh Control Unit counting, address generation and BIU bus cycle gen-
eration in flowchart form.
The nine-bit down-counter loads from the Refresh Interval Register on the falling edge of CLK-
OUT. Once loaded, it decrements every falling CLKOUT edge until it reaches one. Then the
down-counter reloads and starts counting again, simultaneously triggering a refresh request.
Once enabled, the DRAM refresh process continues indefinitely until the user reprograms the Re-
fresh Control Unit, a reset occurs, or the processor enters Powerdown mode. Power-Save mode
divides the Refresh Control Unit clocks, so reprogramming the Refresh Interval Register be-
comes necessary.
The refresh request remains active until the bus becomes available. When the bus is free, the BIU
will run its “dummy read” cycle. Refresh bus requests have higher priority than most CPU bus
cycles, all DMA bus cycles and all interrupt vectoring sequences. Refresh bus cycles also have a
higher priority than the HOLD/HLDA bus arbitration protocol (see “Refresh Operation and Bus
HOLD” on page 7-12).