C-19
INSTRUCTION SET DESCRIPTIONS
INT
Interrupt:
INT
interrupt-type
Activates the interrupt procedure
specified by the interrupt-type
operand. Decrements the stack pointer
by two, pushes the flags onto the
stack, and clears the trap (TF) and
interrupt-enable (IF) flags to disable
single-step and maskable interrupts.
The flags are stored in the format used
by the PUSHF instruction. SP is
decremented again by two, and the CS
register is pushed onto the stack.
The address of the interrupt pointer is
calculated by multiplying interrupt-
type by four; the second word of the
interrupt pointer replaces CS. SP
again is decremented by two, and IP is
pushed onto the stack and is replaced
by the first word of the interrupt pointer.
If interrupt-type = 3, the assembler
generates a short (1 byte) form of the
instruction, known as the breakpoint
interrupt.
Instruction Operands:
INT immed8
(SP)
←
(SP) – 2
((SP) + 1:(SP))
←
FLAGS
(IF)
←
0
(TF)
←
0
(SP)
←
(SP) – 2
((SP) + 1:(SP))
←
(CS)
(CS)
←
(interrupt-type × 4 + 2)
(SP)
←
(SP) – 2
((SP) + 1:(SP))
←
(IP)
(IP)
←
(interrupt-type × 4)
AF –
CF –
DF –
IF
ü
OF –
PF –
SF –
TF
ü
ZF –
Table C-4. Instruction Set (Continued)
Name
Description
Operation
Flags
Affected
NOTE:
The three symbols used in the Flags Affected column are defined as follows:
– the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
ü
the flag is updated after the instruction is executed
Summary of Contents for 80C186XL
Page 1: ...80C186XL 80C188XL Microprocessor User s Manual...
Page 2: ...80C186XL 80C188XL Microprocessor User s Manual 1995...
Page 18: ...1 Introduction...
Page 19: ......
Page 27: ......
Page 28: ...2 Overview of the 80C186 Family Architecture...
Page 29: ......
Page 79: ......
Page 80: ...3 Bus Interface Unit...
Page 81: ......
Page 127: ......
Page 128: ...4 Peripheral Control Block...
Page 129: ......
Page 137: ......
Page 138: ...5 ClockGenerationand Power Management...
Page 139: ......
Page 154: ...6 Chip Select Unit...
Page 155: ......
Page 178: ...7 Refresh Control Unit...
Page 179: ......
Page 193: ......
Page 194: ...8 Interrupt Control Unit...
Page 195: ......
Page 227: ......
Page 228: ...9 Timer Counter Unit...
Page 229: ......
Page 253: ......
Page 254: ...10 Direct Memory Access Unit...
Page 255: ......
Page 283: ......
Page 284: ...11 Math Coprocessing...
Page 285: ......
Page 302: ...12 ONCE Mode...
Page 303: ......
Page 306: ...A 80C186 Instruction Set Additions and Extensions...
Page 307: ......
Page 318: ...B Input Synchronization...
Page 319: ......
Page 322: ...C Instruction Set Descriptions...
Page 323: ......
Page 371: ......
Page 372: ...D Instruction Set Opcodes and Clock Cycles...
Page 373: ......
Page 396: ...Index...
Page 397: ......