Eaton ELC-PB, Programming Manual

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3 . I n s t r u c t i o n S e t
M N050 03003E F or mo re infor ma tio n vi sit:
w w w. e a t o n . c o m
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c) The original quantity of high-speed comparison instructions supported by ELC-PC/PA won’t
decrease due to the addition of a high-speed counter.
d) When high-speed output response times are required for the output of a high-speed
comparison instruction (DHSCS), it is recommended to use Y10 or Y11. If using other
outputs, it will be delayed a scan period. When enabling an interrupt with the high speed
comparison instructions, C243 corresponds to I020, C245 corresponds to I040 and C250,
C255 corresponds to I060.
e) There is a special function allowed for the DHSCR instruction. The field normally containing
a bit address that is cleared when the comparison is true can contain the counter number
instead of a bit address. This allows the counter to be reset when the comparison is true.
This only applies to the counter referenced in the DHSCR instruction, per the following
example: DHSCR K10 C243 C243. Also, this feature only applies to 4 counter numbers,
C243, C245, C250 and C255.
f) Select the frequency mode for the 2-phase 2 input counter mode
Select the 2-phase, 2 input counter mode in ELC-PA/PB/PC/PH series controllers via D1022,
containing four double frequency modes. The content value of register D1022 is loaded at
the first scan when ELC controller is changed from Stop to Run mode.
Device No. Function Explanation
D1022 Double frequency mode is initial set-point when power OFF Æ ON
D1022=K1 Normal frequency mode
D1022=K2 Double frequency mode
D1022=K4 Four times frequency mode
Double frequency mode (2-phase 2 inputs):
a) D1022=K1 (normal frequency)
Signal Diagram
A-phase
B-phase
Counting up
Counting down