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2-64
Special D
Function
ELC
-PB
ELCB
-PB
ELC
-PC
-PA
-PH
ELCM
-PH
- PA
ELC
-PV
OFF
Ø
ON
STOP
Ø
RUN
RUN
Ø
STOP
Type Latched
Factory
setting
D1219
End latched address of register
D2000~D4999
- Y
- Y
- - -
R/W
Yes 4999
D1220
Phase of the 1st group pulse output
CH0 (Y0, Y1)
- -
Y Y
0
- -
R/W
NO 0
D1221
Phase of the 2nd group pulse output
CH1 (Y2, Y3)
- -
Y Y
0
- -
R/W
NO 0
D1222
Time difference between direction
signal and pulse output for the 1st
group pulse CH0 (Y0, Y1) in DRVI,
DDRVI, DRVA, DDRVA, PLSV, DPLSV
- -
- Y
0
- -
R/W
NO 0
D1223
Time difference between direction
signal and pulse output for the 2nd
group pulse CH1 (Y2, Y3) in DRVI,
DDRVI, DRVA, DDRVA, PLSV, DPLSV
- -
- Y
0
- -
R/W
NO 0
D1225
Counting mode of the counter HHSC0
- -
- Y
2
- -
R/W
NO 2
D1226
Counting mode of the counter HHSC1
- -
- Y
2
- -
R/W
NO 2
D1227
Counting mode of the counter HHSC2
- -
- Y
2
- -
R/W
NO 2
D1228
Counting mode of the counter HHSC3
- -
- Y
2
- -
R/W
NO 2
D1129
Phase of the 3rd group pulse output
CH2 (Y4, Y5)
- -
- Y
0
- -
R/W
NO 0
D1130
Phase of the 4th group pulse output
CH3 (Y6, Y7)
- -
- Y
0
- -
R/W
NO 0
D1232
Output pulse number for ramp-down
stop when CH0 mark sensor receives
signals. (Low Word).
- -
Y
Y 0 - -
R/W
NO 0
D1233
Output pulse number for ramp-down
stop when CH0 mark sensor receives
signals. (High Word).
- -
Y Y
0 - -
R/W
NO 0
D1234
Output pulse number for ramp-down
stop when CH1 mark sensor receives
signals (Low Word).
- -
Y Y
0 - -
R/W
NO 0
D1235
Output pulse number for ramp-down
stop when CH1 mark sensor receives
signals (High Word).
- -
Y Y
0 - -
R/W
NO 0
D1236
Output pulse number for ramp-down
stop when CH2 mark sensor receives
signals (Low Word)
- -
- Y
0 - -
R/W
NO 0
D1237
Output pulse number for ramp-down
stop when CH2 mark sensor receives
signals (High Word)
- -
- Y
0 - -
R/W
NO 0
D1238
Output pulse number for ramp-down
stop when CH3 mark sensor receives
signals (Low Word)
- -
- Y
0 - -
R/W
NO 0
D1239
Output pulse number for ramp-down
stop when CH3 mark sensor receives
signals (High Word)
- -
- Y
0 - -
R/W
NO 0
D1240
When interrupt I400/I401/I100/I101
occurs, D1240 stores the low Word of
high-speed counter.
- -
Y -
0 0 - R NO
0
D1241
When interrupt I400/I401/I100/I101
occurs, D1241 stores the high Word of
high-speed counter.
- -
Y -
0 0 - R NO
0
Summary of Contents for ELC-PB
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