Eaton ELC-PB, Programming Manual

Page: 284 / 728

3 . I n s t r u c t i o n S e t
M N050 03003E F or mo re infor ma tio n vi sit:
w w w. e a t o n . c o m
3 - 115
API Mnemonic Operands Function
53 D HSCS
S
1
, S
2
, D
High Speed Counter Set
Bit Devices Word devices Program Steps
Type
OP
X Y M S K H KnX KnY KnM KnS T C D E F
S
1
* * * * * * * * * *
S
2
*
D * * *
DHSCS: 13 steps
ELC ELCB ELCM
PB PC/PA/PH PV PB PH/PA
32 16 P 32 16 P 32 16 P 32 16 P 32 16 P
Operands:
S
1
: Compare value
S
2
: High-speed counter number
D
: Compare result
Description:
(ELC-PB/PC/PA/PH/PV, ELCB-PB)
1. All high-speed counters use an interrupt process; therefore all compare results
D
are
updated immediately.
2. DHSCS instruction compares the current value of the selected high-speed counter
S
2
against a selected compare value
S
1
. When the counters current value equals
S
1
, then
D
=
ON. Once set to ON if values
S
1
and
S
2
are not longer equal,
D
will still be ON.
3. If for example
D
is specified as Y0~Y7 and, when
S
1
and
S
2
are equal, the compare result
will immediately energize output Y0~Y7... If M and S addresses are used, they are also
immediately updated independent of the program scan. Interrupt pointers can also be used
for
D
, to execute an interrupt subroutine when
S
1
and
S
2
are equal
4. Operand limitation:
Operand
S
2
for ELC-PB, ELCB-PB must be C235~C238, C241~C244, C246~C249,
C251~C254. Operand
S
2
for ELC-PC/PA must be C235~C244, C246~C249, C251~C254.
Operand
S
2
for ELC-PH must be C235~ C255.
Interrupt pointers I010 to I060 can be used for
D
, but ELC-PB, ELCB-PB models do not
support these interrupts.
ELC-PB/PC/PA/PH, ELCB-PB series controllers do not support E, F index registers for
D
5. Flags: M1289 ~ M1294 are used to inhibit interrupts for the high speed counters in ELC-PV
series. See Program Example 3 for more details.
Program Example 1:
If M0=ON, the DHSCS instruction starts to operate. Y0 is turned ON immediately when C235’s
present value goes from 99
→
100 or from 101
→
100, and will remain on.