Eaton ELC-PB, Programming Manual

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E L C P r o g r a m m i n g M a n u a l
F o r m o r e i nf o r m a t i o n v i sit :
w w w. e a t o n . c o m
MN05003003E
3-276
API Mnemonic Operands Function
96 TMR
S
1
, S
2
Timer
Bit Devices Word devices Program Steps
Type
OP
X Y M S K H KnX KnY KnM KnS T C D E F
S
1
*
S
2
* *
TMR: 5 steps
ELC ELCB ELCM
PB PC/PA/PH PV PB PH/PA
32 16 P 32 16 P 32 16 P 32 16 P 32 16 P
Operands:
S
1
: Timer number (T0~T255)
S
2
: Preset value (K0~K32,767, ELC-PB, ELCB-PB: D0~D599,
ELC-PC/PA/PH: D0~D4,999, ELC-PV, ELCM-PH/PA: D0~D9,999)
Description:
When the TMR instruction is executed, the timer is energized and will start timing. When the preset
value of the timer is reached (accumulated value >= preset value), the timer done bit will be set. The
timer done bit for any timer must use a bit instruction addressed with the timer number (T5 for
example). The accumulative value of a timer must be used in a word type instruction and is also
addressed with the timer number (T5 for example).
A timer’s time base is determined by the timer number. Each type of ELC controller contains a
different number of timers, so to determine the time base of a timer, refer to the memory maps for
the various controllers located early in Chapter 2. For example, for all controllers timer T0 is a
100ms time base timer. This means that if the preset is K200, timer T0 will be a 20 second timer
(200 x 100ms = 20 seconds). There are also 10ms and 1ms time base timers for most ELC
controllers.
Program example:
Ladder Diagram:
X0
T5 TMR K1000
Instruction: Operation:
LD X0 ; Load A contact of X0
TMR T5 K1000
; T5 timer Setting is K1000