Eaton ELC-PB, Programming Manual

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E L C P r o g r a m m i n g M a n u a l
F o r m o r e i n f o r m a t i o n v i s i t : w w w. e a t o n . c o m M N 0 5 0 0 3 0 0 3 E
3 - 5 0 0
API Mnemonic Operands Function
207 CSFO S, S
1
, D Catch Speed and Proportional Output
Bit Devices Word devices Program Steps
Type
OP
X Y M S K H KnX KnY KnM KnS T C D E F
S
1
*
S
2
*
S *
CSFO: 7 steps
ELC ELCB ELCM
PB PC/PA/PH PV PB PH/PA
32 16 P 32 16 P 32 16 P 32 16 P 32 16 P
Operands:
S : Source address of the signal input (Only X0~X3 are available) S
1
: Sample time setting and
the input speed information D : Output proportion setting and output speed information
Description:
1. When S specifies X0, the ELC only uses the X0 input point and its associated high speed
pulse output: Y0. When S specifies X1, the ELC uses X0 (A phase) and X1 (B phase) input
points and their associated outputs: Y0 (Pulse) / Y1 (Dir). When S specifies X2, the ELC only
uses the X2 input point and its associated high speed pulse output: Y2. When S specifies X3,
the ELC uses X2 (A phase) and X3 (B phase) input points and their associated outputs: Y2
(Pulse) / Y3 (Dir).
2. The execution of CSFO requires a hardware high speed counter function as well as the high
speed output function. Therefore, when program scans the CSFO instruction with high speed
counter input points (X0, X1) or (X2, X3) enabled by with the DCNT instruction, or high speed
pulse outputs (Y0, Y1) or (Y2, Y3) enabled by some other high speed output instructions, the
CSFO instruction will not be activated.
3. If S specifies X1 / X3 with 2-phase 2 inputs, the counting mode is fixed at 4-times frequency.
4. During the pulse output process of Y0 or Y2, special registers (D1031, D1330 / D1337, D1336)
for storing the current number of output pulses will be updated when program scans the
instruction.
5. S
1
occupies 4 consecutive 16-bit registers. S
1
+0 specifies the sample time, i.e. when S
1
+0
uses K1, the ELC catches the speed every time when 1 pulse is sent. Valid range for S
1
+0 in
1-phase 1-input mode: K1~K100, and in 2-phase 2-input mode: K2~K100. If the specified
value exceeds the valid range, the ELC will take the lower/upper limit value as the set value.
Sample time can be changed during ELC operation, however the modified value will not take
effect until the instruction is scanned. S
1
+1 indicates the latest speed sampled by the ELC
(Read-only). Units: 1Hz. Valid range:
±
10kHz. S
1
+2 and S
1
+3 indicate the accumulated value
of pulses as a 32-bit value (Read-only).
6. S
1
+0 specifies the sample time. The value of the sample time is recommended to be larger
when the input speed increases, so as to achieve a higher accuracy for trapping the speed.