BAT32G1x9 user manual | Chapter 23 LCD bus interface
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Rev.1.02
23.4.3
Write the LCD bus
This section describes typical 16-bit and 8-bit write timing for LCD buses.
(1). 16-bit write
A 16-bit write transfers two 8-bit data to an external LCD controller/driver.
Figure 23-9
Write contiguous
16 bits
timing
(80
mode: LBTCTL. IMD=0)
LBWST=5,LBCYC=8,LBCTL. TCIS=0
Description: Timing diagrams are for feature description purposes only and have no association with the actual
hardware implementation.
(a) The order of the run
<1> the first set of 16 bits of data from the LCD is written to the LBDATA registers. Operating the write
interface registers over the internal bus requires some clocks. The busy flag bits then are set up until the data is
copied to the write buffer.
<2> t h e c o n t e n t s o f t h e L B D A T A r e g i s t e r a r e c o p i e d t o t h e w r i t e b u f f e r .
LBCTL. The BYF flag bit is then cleared and an INTLDB valid signal for one clock cycle is output. Transmission
on the LCD bus interface starts at 8 bits of data 0. The flag bit LBCTL.TPF is placed, indicating that a
transmission is in progress.
<3> DMA triggered by INTLDB writes a second set of 16 bits of data to LBDATA. By querying the busy flag bit
LBCTL.BYF, the CPU can also write this 16 bits of data. Operating the internal bus to write lbDATA registers and
enable LBCTL.BYF to be set up also requires some clock cycles.
<4> S in c e t h e L C D b u s in t e r f a c e is s t ill in t r a n s it , t h e contents of the LBDATA register cannot be
copied immediately to the write buffer, LBCTL. BYF remains in the state of being placed.
<5> After the LCD bus interface transfer ends, the write buffer is again populated with data from the LBDATA
registers. Busy flag bit LBCTL. BYF is cleared to zero while outputting an INTLDB valid signal for one clock cycle.
Each time data is copied from LBDATA to the write buffer, a transfer to the external LCD controller is
initiated.
