Cmsemicon BAT32G1 9 Series, Руководство пользователя

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BAT32G1x9 user manual | Chapter 3 System structure
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Chapter 3 System structure
3.1 overview
This product system consists of the following parts:
⚫
2 AHB bus Master:
- Cortex-M0+
- Enhanced DMA
⚫
4 AHB Bus Slaves:
- FLASH memory
- SRAM memory 0
- SRAM memory 1
- AHB to APB Bridge, which contains all APB interface peripherals
Figure 3-1 Schematic diagram of the system structure
Cortex-M0+
DMA
bus
matrix
flash
memory
sram
memory 0
sram
memory 1
AHB to APB
bus bridge
AHB bus
Peripheral
hardware
APB bus
DMA bus
system bus
•
System Bus: This bus connects the system bus (peripheral bus) of the Cortex-M0+ core to a bus matrix
that coordinates access between the core and the DMA.
•
DMA bus: This bus connects the DMA's AHB master interface to a bus matrix that coordinates CPU and
DMA access to SRAM, flash memory, and peripherals.
•
Bus Matrix: The bus matrix coordinates the access arbitration between the core system bus and the DMA
master bus, with a fixed priority and a high DMA priority.
•
AHB to APB Bridge: AHB to APB Bridge provides a synchronous connection between the AHB and APB
buses. Refer to Table 3-1 for address mappings for different peripherals connected to each bridge.