Cmsemicon BAT32G1 9 Series, Руководство пользователя

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BAT32G1x9 user manual | Chapter 20 Serial interface IICA
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809 / 1149 Rev.1.02
FIG 20-
31 Communication example of a master device → slave device
(Master: Select 9 clocks to wait, Slave: Choose 9 clocks to wait) (4/4).
(4) Data ~ restart condition ~ address
master control
IICAn
ACKDn
（
ACKdetection
）
WTIMn
（
8 or 9 clock cycles
waiting
）
H
ACKEn
（
ACK control
）
MSTSn
（
communicdat
ion state
）
STTn
（
ST trigger
）
H
SPTn
（
SP trigger
）
WRELn
（
release from
wait
）
L
INTIICAn
（
interrupt
）
TRCn
（
transmit
/reception
）
bus
SCLAn(bus)
（
Clock line
）
SDAAn(bus)
（
data line
）
slave
IICAn
ACKDn
（
ACKdetectio
n
）
STDn
（
STdetection
）
SPDn
（
SPdetection
）
WTIMn
（
8 or 9 clock cycles
waiting
）
ACKEn
（
ACK
control
）
MSTSn
（
communicdat
ion state
）
WRELn
（
release from
wait
）
INTIICAn
（
interrupt
）
TRCn
（
transmit
/reception
）
H
H
L
L
：
slave device waits
：
master device and slave device waits
L
note2
：
master device waits
H
L
H
D
1
2 D
1
1
D
1
0
D
1
3
AD6
AD5 AD4 AD3 AD2 AD1
slave address
restart start
condition
note1
ACK
<1>
<2>
<3>
Note: 1 After the release of the restart condition, the time from which the SCLAn pin signal rises to generate the start
condition is at least
4.7μs
when
set to standard mode and at least
0.6μs
when set to fast mode
.
2. To lift the wait during slave reception, the IICAn
must be
placed in the "FFH" or WRELn position.