Cmsemicon BAT32G1 9 Series, Руководство пользователя

Страница: 331 / 1149

BAT32G1x9 user manual | Chapter 10 Timer M
www.mcu.com.cn
331 / 1149 Rev.1.02
Figure 10-17 Format of timer M control register 0 (TMCR0) [Reset Synchronous PWM Mode].
Address: 0x40042A70 after reset: 00H R/W
symbol
TMCR0
CCLR2 CCLR1 CCLR0
Clear selection for the TM0 counter
"001B" must be set (clear the TM0 register when matching the TMGRA0 register).
CKEG1 CKEG0 Select
Note 1
for the external clock edge
0 0 Count on the rising edge.
0
1
Count on the falling edge.
1 0
Count on the bilateral edge.
Other than the
above Prohibit settings.
TCK2 TCK1 TCK0 Count the selection of sources
0
0 0
f
CLK
0 0 1
f
CLK
/2
0 1 0
f
CLK
/4
0 1 1
f
CLK
/8
1 0 0
f
CLK
/32
1 0 1
Input
note 2
for TMCLK
Other than the above Prohibit settings.
Note 1. The TCK2~TCK0 bit is "101B" (the input to TMCLK
) and
the STCLK bit is "1" Valid when (external clock
input valid).
2. Valid when the STCLK bit of the TMFCR
register is
"1" (the external clock input is valid).
7 6 5 4 3
2 1
0
CCLR2 CcLR1 CCLR0 CKEG1 CKEG0 TCK2 TCK1 TCK0