BAT32G1x9 user manual | Chapter 6 Universal timer unit Timer4/8
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Rev.1.02
6.5 The operation of the counter
6.5.1
Count clock (f
TCLK
).
The general-purpose timer unit's counting clock (f
TCLK
) selects any of the following clocks by the CCSmn
bit of the timer mode register mn (TMRmn).
•
CKSmn0 bits and
CKSmn1
bits specify the operating clock (f
MCK
).
•
The effective edge of the input signal at the TImn pin
The universal timer unit is designed to operate synchronously with the f
CLK
, so the timing of the count clock
(f
TCLK
) is as follows.
(1) Select the case (CCSmn=0) specified by the CKSmn0 bit and CKSmn1 bits specified for the operating
clock (f
MCK
).
Depending on the setting of the timer clock select register m (TPSm), the count clock (f
TCLK
) is f
CLK
~f
CLK
/2
15
。
However, when the division of f
CLK
is selected, the clock selected by the TPSm register is a signal that starts
with only 1 f
CLK
cycle high starting on the rising edge. When f
CLK
is selected, it is fixed to high.
To achieve synchronization with the f
CLK
, the timer count register mn (TCRmn) delays the count by 1 f
CLK
clock starting from the rising edge of the count clock. It is called "counting on the rising edge of the counting
clock" for convenience.
Figure 6-24
f
CLK
and count clock (f
TCLK
) (in the case of CCSmn=0).
f
CLK
f
CLK
/2
f
CLK
/4
f
CLK
/8
f
CLK
/16
f
TCLK
(= f
MCK
=CKmn)
Remarks: 1
△
: Counts the rising edge of the clock
▲: Synchronization, increment/decrement of the
counter
2. f
CLK
:
CPU/peripheral hardware clock
