Cmsemicon BAT32G1 9 Series, Руководство пользователя

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BAT32G1x9 user manual | Chapter 17 Comparator
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17.4.12
The event signal output to the linkage controller (EVENTC).
In the same way that interrupt requests are generated, an event signal is generated to eventc by detecting
the output edge of the digital filter set by the COMFIR register. However, unlike interrupt requests, it is
independent of the CiIE bit of the COMCCR register and always outputs an event signal to EVENTC. The
selection of event output targets and the stop of event links must be set through EVENTC's ELSELR 20
registers and ELSELR21 registers.
Figure 17-14 Operation of a digital filter, interrupt request, and output event signal to
EVENTC
input of
digital filter
sample timing
sequence
output of
digital filter
interrupt
request, output
event signal to
EVENTC.
NOTE
as long as 1 out of 3 times the
signal is not identical, the signnal
will be discarded as noise, output
remain unchanged.
if 3 times signals are
identical, then it is considered
as signal change and
reflected to output.
as long as 1 out of 3 times the
signal is not identical, the signnal
will be discarded as noise, output
remain unchanged.
if 3 times signals are identical, then it is
considered as signal change and reflected to
output.
when input signal of
digital filter changes,
output single trigger
pulse
directly output the
input singal of
digital filter
inverted output of the
input singal of digital
filter
when input signal of digital filter changes, output single
trigger pulse
directly output the input singal of digital filter
inverted output of the input singal of digital filter
(A)
(B)
(C)
(D)
(E)
(F)
Note That when the CiIE bit (i=0, 1) is "1", the interrupt request and the
event signal output
to
EVENTC are the same waveform. When the CiIE bit (i=0, 1) is "0", only the
interrupt request is fixed to "0".
The waveform of (A) ,( B ) , (C) is the CiFCK bit of the COMFIR register ( i = 0 , 1 ) is " In the case of 00B"
(without a digital filter), the waveforms of (D), (E), (F) are the CiFCK of the COMFIR registers When the bits
(i=0, 1) are "01B", "10B", or "11B" (with digital filter). (A) and (D) are the cases where the CiEDG bit is "1"
(bilateral edge), (B), (E). Is the case where the CiEDG bit is "0" and the CiEPO bit is "0" (rising edge), (C), (F).
Is the case where the CiEDG bit is "0" and the CiEPO bit is "1" (falling edge).