BAT32G1x9 user manual | Chapter 4 Clock generation circuit
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Rev.1.02
4.6.3
Example of setting up the XT1 oscillation circuit
After the reset is released, the CPU/Peripheral Hardware Clock (f
CLK
) must be running at a high-speed
internal oscillator clock. Thereafter, if the XT1 oscillation clock is changed, the mode control register (OSMC),
clock operating mode control register (CMC), and clock operating state control register (CSC) are provided
through the sub-system clock The oscillation circuit is set up and the oscillation start is controlled, and the XT1
oscillation clock is set to f
CLK
via the system clock control register (CKC).
【
Register Setting
】
Registers must be set in the order of (1) to (5).
(1) In deep sleep mode or the CPU running on the subsystem clock, the RTCPC bit must be set to "1" when
the real-time clock and the 15-bit interval timer are running at the sub-system clock (ultra-low consumption
current).
7
6
5
4
3
2
1
0
OSMC
(2) Place the OSCSELS position of the CMC register "1" so that the XT1 oscillation circuit runs.
7
6
5
4
3
2
1
0
Cmc
AMPHS0 bit and AMPHS1 bit: Sets the oscillation mode of the XT1 oscillation circuit.
(3) Clear the XTSTOP bit of the CSC register to "0" so that the XT1 oscillation circuit begins to oscillate.
7
6
5
4
3
2
1
0
CSC
(4) It is necessary to wait for the oscillation stabilization time required by the subsystem clock through
software and timer functions, etc.
(5) Set the XT1 oscillation clock to the CPU/peripheral hardware clock through the CSS bit of the CLC
register.
7
6
5
4
3
2
1
0
CKC
RTCLPC
0/1
0
0
WUTMMCK0
0
0
0
0
0
EXCLK
0
OSCSEL
0
EXCLKS
0
OSCSELS
1
0
AMPHS1
0/1
AMPHS0
0/1
AMPH
0
MSTOP
1
XTSTOP
0
0
0
0
0
0
HIOSTOP
0
CLS
0
CSS
0
MCS
0
MCM0
1
0
0
0
0
MSTOP
0
XTSTOP
1
0
0
0
0
0
HIOSTOP
0
