BAT32G1x9 user manual | Chapter 8 Timer B
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Rev.1.02
6
5
4
3
2
1
0
0
TBTCK2
TBTCK1
TBTCK0
7
8.3.4 Timer B Control Register (TBCR).
The TBCR register must be written in a state where the TBSTART bit of the TBMR register is "0" (stop
count).
Figure 8-5
Format of timer B control register (TBCR).
Address: 40042652H
after reset:
00H R/W
symbol
TBCR
TBCCLR1
TBCCLR0
Clear source selection for TB registers
0
0
Not allowed to clear.
0
1
Clears when TBGRA's input captures or compares matches.
1
0
Clears when the input of the TBGRB
is captured or compared to match.
Other than the above
Prohibit settings.
TBCKEG1
TBCKEG0
Select for the valid edges of the external clock
notes 1 and 2
0
0
Count on the rising edge.
0
1
Count on the falling edge.
1
0
Count on the
bilateral edges of the rising/falling edges.
Other than the above
Prohibit settings.
TBTCK2
TBTCK1
TBTCK0
Select for the count source
Note
1
0
0
0
f
CLK
0
0
1
f
CLK
/2
0
1
0
f
CLK
/4
0
1
1
f
CLK
/8
1
0
0
f
CLK
/32
1
0
1
Input to TBCLK0
1
1
1
Input to TBCLK1
Other than the above
Prohibit settings.
Note 1
In the phase count mode, the settings of
TBTCK0~TBTCK2
bit,
TBCKEG0
bit and
TBCKEG 1
bit are invalid, and
the phase count mode is preferred.
2. When TBCKEG0 bits and TBCKEG1 bits are set to an external clock (TBCLK0, TBCLK1) in TBTCK0~TBTCK2
bits valid, otherwise it is not valid.
