Cmsemicon BAT32G1 9 Series, Руководство пользователя

Страница: 111 / 1149

BAT32G1x9 user manual | Chapter 4 Clock generation circuit
www.mcu.com.cn
111 / 1149 Rev.1.02
Table 4-3 Example of CPU clock transfer and SFR register setting (4/5).
(9) The CPU shifts from subsystem clock operation (D) to high-speed system clock operation (C).
(SFR registers are set in order).
Setting flag for the SFR
register
State transition
OSTS
register
CSC registers
OSTC registers
CKC registers
MSTOP CSS
(D) (C)
(X1c
lock:1MHz≤f
X
≤10MHz)
note
0
Confirmation
is required
0
(D) (C)
(X1Clock:10MHz
＜
f
X
≤20MHz)
note
0
Confirmation
is required
0
(D) (C)
(External Master Clock)
note
0
No
confirmation is
required
0
Not required during high-speed system clock operation.
Note The oscillation settling time of the Oscillation Settling Time Selection Register (OSTS) must be set as follows:
• The oscillation settling time of the State Register (OSTC) of the Expected Oscillation Settling Time Counter
≤ the Oscillation Settling Time of the OSTS Register Settings
Note The clock must be set after the supply voltage reaches the set clock operatable voltage (see
data sheet).
(10) • The CPU is transferred to sleep mode (E) while the high-speed internal oscillator clock is running(B).
• The CPU is transferred to sleep mode (F) during high-speed system clock operation (C).
• The CPU is transferred to sleep mode (G) while the subsystem clock is running (D).
State transition Content of configuration
(B) (E)
(C) (F)
(D) (G)
Execute WFI instructions.
Note Table 4-3of (A) ~ (I) corresponds to Figure
4-22
of (A) ~ ( I)
。