BAT32G1x9 user manual | Chapter 6 Universal timer unit Timer4/8
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Rev.1.02
Fig6-64 Operating steps for single trigger pulse output function (1/2).
software operation
hardware state
Timer Unit m input clock is in stopped state (stop providing clock, not able to write
into registers)
set TM4mEN bit of peripheral enable register 0
(PER0) to '1'
Timer Unit m input clock is in active state, all channels in operation stopped state.
(start providing clock, Start to provide clock, can write to each register)
configure Timer clock selection register m(TPSm),
confirm CKm0~CKm3 clock frequency
set corresponding bit of noise filter enable register 1
(NFEN1) to 1'.
Configure Timer mode registers mn,mp of 2
channels (TMRmn, TMRmp) (confirm channel
operation mode).
Set master control channel Timer data register mn
(TDRmn) configure output delay time, and set slave
channel TDRmp register pulse width.
channel in operation stopped state
(providing clock, consume portion of power)
slave channel configuration
set TOMmp bit of timer output mode register
m(TOMm) to '1' (slave channel output mode).
Configure TOLmp bit.
Configure TOmp bit and confirm TOmp otuput initial
voltage.
Set TOEmp bit to '1', enable TOmp output.
Set port regsiter and port mode regsiter to '0'.
T0mp pin in Hi-Z output state.
When port mode register set to output mode and port register as '0', output T0mp
initial configured voltage level.
Because channel is in operation stopped state, thus T0mp remains unchange.
T0mp pin output T0mp configured voltage level.
Timer 4 initial
configuration
Channel Initial
configuration
