Cmsemicon BAT32G1 9 Series, Руководство пользователя

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BAT32G1x9 user manual | Chapter 24 Enhanced DMA
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1025 / 1149 Rev.1.02
DMAENi2
DMA boot enable i2
0 Disable startup.
1
Allow startup.
Depending on the condition in which the end-of-transfer interrupt occurs, the DMAENi2 bit becomes "0"
(disables startup).
DMAENi1
DMA boot enable i1
0
Disable startup.
1
Allow startup.
Depending on the condition in which the end-of-transmit interrupt occurs, the DMAENi1 bit becomes "0"
(disables startup).
DMAENi0
DMA boot enable i0
0
Disable startup.
1
Allow startup.
Depending on the condition under which the end-of-transfer interrupt occurs, the DMAENi0 bit becomes
"0" (disables startup).
Table 24-6 Interrupt source corresponds to DMAENi0~DMAENi7 bits
register
DMAENi7
bits
DMAENi6 bit
DMAENi5
bits DMAENi4
bits DMAENi3
bits DMAENi2
bits
DMAENi1 bit
DMAENi0
bits
DMAEN0
INTP6
INTP5 INTP4 INTP3 INTP2 INTP1 INTP0
The LCD bus
transfer ends
with an
interrupt
DMAEN1
Transmit end
received by
UART2/Trans
mit End for
CSI21 or
Transmit End
for Buffer
Null/IIC21 Transfer end
for UART1
transmission/t
ransfer end
for CSI10 or
transfer end
for buffer
null/IIC10 Transmit end
received by
UART1/Trans
mit End of
CSI11 or
Transmit End
of Buffer
Null/IIC11 Transfer end
for
UART0/trans
fer end for
CSI00 or
transfer end
for buffer
null/IIC00 Transmit end
received by
UART0/Tran
smit End for
CSI01 or
Transmit End
for Buffer
Null/IIC01
End of A/D
conversion
KEY input
INTP7
DMAEN2
15-bit interval
timer
interrupt
The end of the
count or the
end of the
capture of
channel 3 of
the timer array
unit 0
The end of the
count or the
end of capture
for channel 2
of the timer
array unit 0
The end of
the count or
the end of
the capture
of channel 1
of the timer
array unit 0 The end of
the count or
the end of
the snap of
channel 0 of
the timer
array unit 0
High-speed
SPI0
communicati
on end note
IICA0
communicati
on ended
Transfer end
for UART2
transmission/
transfer end
for CSI20 or
transfer end
for buffer
null/IIC20
DMAEN3
The
comparison of
TimerM
matches A1
The
comparison
of timerM
matches D0 The
comparison
of TimerM
matches C0 The
comparison
of TimerM
matches B0 The
comparison
of TimerM
matches A0
Overflow of
TimerC
High-speed
SPI1
communicati
on end
note
Flash
erase/write
end
DMAEN4
Comparator
detection 1
The
comparator
detects 0
TimerA
Overflow
The
comparison
of TimerB
matches B The
comparison
of TimerB
matches A The
comparison
of TimerM
matches D1 The
comparison of
TimerM
matches C1 The
comparison of
TimerM
matches B1
Note: LCDB, SPIHS0, SPIHS1 are proprietary to BAT32G179, so when BAT32G139 products are used, bit 0 of DMAEN0,
bit 2 of DMAEN2 and bit 1 of DMAEN3 must be placed at 1'b0
。
Note i = 0 ~ 4