BAT32G1x9 user manual | Chapter 8 Timer B
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Rev.1.02
8.6.4 Setup steps for TBIO0 pins and TBIO1 pins
After reset, the multiplexed I/O ports on the TBIO0 pin and TBIO1 pins are used as input ports.
•
When you want to output from the TBIO0 pin and TBIO1 pins, you
must follow the steps below to set it up.
Change steps
(1) Make the settings allowed for the mode, initial value, and output (because both
the initial value and the allowed setting are made via SFR). (2) Place the position of
the port register corresponding to the TBIO0 pin and the TBIO1 pin "0".
(3) Set the bits of the port mode registers corresponding to the TBIO0 pins and TBIO1 pins to
output mode (starting with the TBIO0 pins and TBIO1 pins).
(4) Start counting (TBMR registers have a TBSTART bit of "1").
•
To change the bit of the port mode register corresponding to the TBIO0 pin and TBIO1 pin from
output mode to input mode, you must follow the steps below to set it.
Change steps
(1) Set the bit of the port mode register corresponding to the TBIO0 pin and the TBIO10 pin to input
mode (starting with the TBIO0 pin and TBIO1 pin).
(2) Set to input capture function.
(3) Start counting (TBMR registers have a TBSTART bit of "1").
• When switching the TBIO0 pin and TBIO1 pin from output mode to input mode, input capture operation
may be performed depending on the state of the pin. Edge detection after at least 2 CPU clock cycles
when no digital filter is used; When using digital filters, up to 5 sampling clock cycles of digital filters
are required for edge detection.
8.6.5 External clocks TBBCLK0 and TBBCLK1
The pulse width of the external clock input to the TBCLKj pin (j=0, 1) must be at least 3 timer B operating
clock (f
CLK
) cycles.
8.6.6 Read and write access to SFR
To set timer B, you must first place the TMBEN position of the PER1 register "1". When the TMBEN bit is
"0", the write operation of the control register of timer B is ignored, and the read values are initial values
(except for the port registers and port mode registers).
(1)
TBMR registers
When switching the clock of a digital filter, you must follow these steps to set it up:
(a)
Set the TBDFA bits and TBDFB bits (TBIO0 pins and) of the TBBMR registers in the state where the
TBSTART bit is "0" (stop count). Digital filter function select bit on the TBIO1 pin), TBDFCK0 bit of
TBMR register, and TBDFCK1 bit of TBMR register (clock select bit of digital filter function).
(b)
Place TBSTART at position "1".
However, if the digital filter is not set and the TBDFCK1 and TBDFCK0 bits that are reset to "00B" after
reset are not changed, one-time setting can be made.
In addition to the external input pins (TBIO0, TBIO1), event events for the EVENTC input can be selected
as the operating source for input capture. When this feature is not used, the TBELCICE position of the TBMR
register must be set to "1" and the input snap function must be set (the effective edge of the input snap is the
rising edge (TBIOB2~ TBIOB0=100B) )
。
This function is invalid when using the output comparison function in
PWM mode or timer mode (TBPWM=1, TBIOB2=0).
(2)
TB registers
• The write operation priority of the TBMR registers is timer B operating condition resulting in a count
reset.
